# US 2026/0100233 A1 · Nonvolatile memory device and memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100233 A1 - Document ID: US20260100233A1 - Status: Published application - Kind: A1 - Application number: 19/313,173 - Filed: 2025-08-28 - Published: 2026-04-09 - Earliest claimed: 2024-10-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sangyun Kim; Hyunsuk Kang; Kyoungtae Kang; Dongku Kang; Youngdon Choi - Web page: https://patentgrep.com/patent/US20260100233A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/106: {Data output latches} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 16/24: Bit-line control circuits - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A first group of FIFO registers are connected to page buffer circuits, respectively. The second group of FIFO registers are connected to the first group of FIFO registers. The multiplexer selects one of a plurality of sub data output from the second group of FIFO registers. The control circuit, in response to a first read command, performs a first read operation by sensing a first data stored in a first memory plane and by storing the first sensed data in a corresponding first set of FIFO registers as a first sub data and, in response to a second read command, performs a second read operation by sensing a second data stored in a second memory plane as a second sub data while performing a first output operation to output the first sub data through a multiplexer and a data input/output circuit in response to a first data output command. ## Claims ### Claim 1 A nonvolatile memory device comprising: a plurality of page buffer circuits corresponding to a plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines; a first group of first-in/first-out (FIFO) registers connected to the plurality of page buffer circuits, respectively; a second group of FIFO registers connected to the first group of FIFO registers, respectively; a multiplexer configured to select one of a plurality of sub data output from the second group of FIFO registers, in response to a plane selection signal; and a control circuit configured to control the plurality of page buffer circuits, the first group of FIFO registers, and the second group of FIFO registers, wherein the control circuit is configured to: perform a first read operation, in response to a first read command, wherein the first read operation comprises sensing a first data stored in a first memory plane among the plurality of memory planes through a first page buffer circuit and storing the first sensed data in a corresponding first set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a first sub data; and perform a second read operation, in response to a second read command, wherein the second read operation comprises sensing a second data stored in a second memory plane among the plurality of memory planes through a second page buffer circuit and storing the second sensed data in a corresponding second set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a second sub data while performing a first output operation to output the first sub data to a circuit outside of the nonvolatile memory device through the multiplexer and a data input/output circuit in response to a first data output command. ### Claim 2 (depends on 1) The nonvolatile memory device of claim 1, wherein the first group of FIFO registers are disposed adjacent to the plurality of page buffer circuits, and wherein the second group of FIFO registers are disposed adjacent to the multiplexer. ### Claim 3 (depends on 1) The nonvolatile memory device of claim 1, wherein the control circuit is configured to perform the first output operation immediately upon receipt of the first data output command. ### Claim 4 (depends on 1) The nonvolatile memory device of claim 1, wherein the control circuit is configured to: perform a third read operation, in response to a third read command, wherein the first read operation comprises sensing a third data stored a third memory plane among the plurality of memory planes through a third page buffer circuit and storing the second sensed data in a corresponding third set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a third sub data while performing a second output operation to output the second sub data to the circuit outside of the nonvolatile memory device through the multiplexer and the data input/output circuit in response to a second data output command. ### Claim 5 (depends on 4) The nonvolatile memory device of claim 4, wherein the first data stored in the first memory plane and the second data stored in the second memory plane have a same logical unit number. ### Claim 6 (depends on 5) The nonvolatile memory device of claim 5, wherein the control circuit is configured to perform the second output operation immediately upon receipt of the second data output command. ### Claim 7 (depends on 4) The nonvolatile memory device of claim 4, wherein the first data stored in the first memory plane and the second data stored in the second memory plane have different logical unit numbers. ### Claim 8 (depends on 1) The nonvolatile memory device of claim 1, comprising: a plurality of first control clock generators corresponding to the first group of FIFO registers; and a plurality of second control clock generators corresponding to the second group of FIFO registers, wherein the corresponding first set of FIFO registers include a first FIFO register connected to the first page buffer circuit and a second FIFO register connected to the first FIFO register. ### Claim 9 (depends on 8) The nonvolatile memory device of claim 8, wherein the control circuit is configured to perform the first read operation by controlling a first control clock generator among the plurality of first control clock generators and by controlling a second control clock generator among the plurality of second control clock generators. ### Claim 10 (depends on 9) The nonvolatile memory device of claim 9, wherein the first control clock generator is configured to output a first input clock signal and a first output clock signal to the first FIFO register; and wherein the first FIFO register is configured to store the first sensed data output from the first page buffer circuit, based on the first input clock signal, and configured to output the first sensed data to the second FIFO register, based on the first output clock signal. ### Claim 11 (depends on 10) The nonvolatile memory device of claim 10, wherein the second control clock generator is configured to output a second input clock signal and a second output clock signal to the second FIFO register; and wherein the second FIFO register is configured to store the second sensed data output from the first FIFO register, based on the second input clock signal, and configured to output the second sensed data to the multiplexer as the first sub data, based on the second output clock signal. ### Claim 12 (depends on 8) The nonvolatile memory device of claim 8, wherein the control circuit is configured to perform the second read operation by controlling a third control clock generator among the plurality of first control clock generators and by controlling a fourth control clock generator among the plurality of second control clock generators. ### Claim 13 (depends on 8) The nonvolatile memory device of claim 8, wherein the control circuit is configured to, in response to a corresponding read command, control the plurality of page buffer circuits, the plurality of first control clock generators, and the plurality of second control clock generators to cause corresponding data to be sequentially stored in the second group of FIFO registers via the first group of FIFO registers. ### Claim 14 (depends on 13) The nonvolatile memory device of claim 13, wherein the control circuit is configured to, in response to corresponding data output commands, control an output operation such that data stored in the second group of FIFO registers are output immediately. ### Claim 15 (depends on 14) The nonvolatile memory device of claim 14, wherein data stored in the plurality of memory planes have a same logical unit number. ### Claim 16 (depends on 14) The nonvolatile memory device of claim 14, wherein data stored in at least two of the plurality of memory planes have different logical unit numbers. ### Claim 17 (depends on 1) The nonvolatile memory device of claim 1, wherein: the plurality of memory planes are disposed in a first semiconductor layer, the plurality of page buffer circuits, the first group of FIFO registers, the second group of FIFO registers, and the multiplexer are disposed in a second semiconductor layer, and the second semiconductor layer is stacked in a vertical direction with respect to the first semiconductor layer. ### Claim 18 A memory system comprising: a nonvolatile memory device configured to output a read data; and a memory controller configured to control the nonvolatile memory device and correct errors in the read data, wherein the nonvolatile memory device comprises: a plurality of page buffer circuits corresponding to a plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines; a first group of first-in/first-out (FIFO) registers connected to the plurality of page buffer circuits, respectively; a second group of FIFO registers connected to the first group of FIFO registers, respectively; a multiplexer configured to select one of a plurality of sub data output from the second group of FIFO registers, in response to a plane selection signal; and a control circuit configured to control the plurality of page buffer circuits, the first group of FIFO registers and the second group of FIFO registers, wherein the control circuit is configured to: perform a first read operation, in response to a first read command, wherein the first read operation comprises sensing a first data stored in a first memory plane among the plurality of memory planes through a first page buffer circuit and storing the first sensed data in a corresponding first set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a first sub data; and perform a second read operation, in response to a second read command, wherein the second read operation comprises sensing a second data stored in a second memory plane among the plurality of memory planes through a second page buffer circuit and storing the second sensed data in a corresponding second set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a second sub data while performing a first output operation to output the first sub data to the memory controller through the multiplexer and a data input/output circuit in response to a first data output command. ### Claim 19 (depends on 18) The memory system of claim 18, wherein the memory controller includes: an error correction code (ECC) engine configured to correct errors in the read data by performing an ECC decoding on the read data; and a processor configured to control the ECC engine. ### Claim 20 A nonvolatile memory device comprising: a memory cell array including a plurality of memory planes; a plurality of page buffer circuits corresponding to a plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines; a first group of first-in/first-out (FIFO) registers connected to the plurality of page buffer circuits, respectively; a second group of FIFO registers connected to the first group of FIFO registers, respectively; a multiplexer configured to select one of a plurality of sub data output from the second group of FIFO registers, in response to a plane selection signal; and a control circuit configured to control the plurality of page buffer circuits, the first group of FIFO registers and the second group of FIFO registers, wherein the control circuit is configured to: perform a first read operation, in response to a first read command, wherein the first read operation comprises sensing a first data stored in a first memory plane among the plurality of memory planes through a first page buffer circuit and storing the first sensed data in a first FIFO register among the first group of FIFO registers and in a second FIFO register among the second group of FIFO registers as a first sub data; and perform a second read operation, in response to a second read command, wherein the second read operation comprises sensing a second data stored in a second memory plane among the plurality of memory planes through a second page buffer circuit and storing the second sensed data in a third FIFO register among the first group of FIFO registers and in a fourth FIFO register among the second group of FIFO registers as a second sub data while performing a first output operation to output the first sub data to a circuit outside of the nonvolatile memory device through the multiplexer and a data input/output circuit in response to a first data output command, wherein the control circuit is configured to perform the first output operation immediately upon receipt of the first data output command.