# US 2026/0100231 A1 · Dynamic program pulse widths for different sub-blocks in a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100231 A1 - Document ID: US20260100231A1 - Status: Published application - Kind: A1 - Application number: 19/310,714 - Filed: 2025-08-26 - Published: 2026-04-09 - Earliest claimed: 2024-10-08 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Yu-Chung Lien; Zhenming Zhou - Web page: https://patentgrep.com/patent/US20260100231A1 ## CPC - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a memory array with a plurality of blocks and control logic to initiate a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array. The control logic further identifies a categorization of the first sub-block, determines a corresponding program pulse width based on the categorization of the first sub-block, and causes a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation. ## Claims ### Claim 1 A memory device comprising: a memory array comprising a plurality of blocks; and control logic, operatively coupled with the memory array, to perform operations comprising: initiating a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array; identifying a categorization of the first sub-block; determining a corresponding program pulse width based on the categorization of the first sub-block; and causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the categorization of the first sub-block is based on a physical location of the first sub-block within the one of the plurality of blocks. ### Claim 3 (depends on 1) The memory device of claim 1, wherein each of the plurality of blocks comprises a respective plurality of sub-blocks, and wherein each of the respective plurality of sub-blocks has a respective associated categorization. ### Claim 4 (depends on 3) The memory device of claim 3, wherein each respective associated categorization has a different corresponding program pulse width. ### Claim 5 (depends on 3) The memory device of claim 3, wherein each respective associated categorization comprises one of an outer-most sub-block disposed at an edge of one of the plurality of blocks, an inner-most sub-block disposed at a center of the one of the plurality of blocks, or a middle sub-block disposed between the outer-most sub-block and the inner-most sub-block of the one of the plurality of blocks. ### Claim 6 (depends on 1) The memory device of claim 1, wherein determining the corresponding program pulse width comprises determining a predefined period, based on the categorization of the first sub-block, for which the program voltage pulse is to remain at a peak voltage level. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the causing the program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation comprises loading a value indicating the corresponding program pulse width into an associated register. ### Claim 8 A method comprising: initiating a program operation on one or more memory cells in a first sub-block of one of a plurality of blocks of a memory device; identifying a categorization of the first sub-block; determining a corresponding program pulse width based on the categorization of the first sub-block; and causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation. ### Claim 9 (depends on 8) The method of claim 8, wherein the categorization of the first sub-block is based on a physical location of the first sub-block within the one of the plurality of blocks. ### Claim 10 (depends on 8) The method of claim 8, wherein each of the plurality of blocks comprises a respective plurality of sub-blocks, and wherein each of the respective plurality of sub-blocks has a respective associated categorization. ### Claim 11 (depends on 10) The method of claim 10, wherein each respective associated categorization has a different corresponding program pulse width. ### Claim 12 (depends on 10) The method of claim 10, wherein each respective associated categorization comprises one of an outer-most sub-block disposed at an edge of one of the plurality of blocks, an inner-most sub-block disposed at a center of the one of the plurality of blocks, or a middle sub-block disposed between the outer-most sub-block and the inner-most sub-block of the one of the plurality of blocks. ### Claim 13 (depends on 8) The method of claim 8, wherein determining the corresponding program pulse width comprises determining a predefined period, based on the categorization of the first sub-block, for which the program voltage pulse is to remain at a peak voltage level. ### Claim 14 (depends on 8) The method of claim 8, wherein the causing the program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation comprises loading a value indicating the corresponding program pulse width into an associated register. ### Claim 15 A memory device comprising: a memory array comprising a plurality of blocks; and control logic, operatively coupled with the memory array, to perform operations comprising: initiating a program operation on one or more memory cells in each of a plurality of sub-blocks of one of the plurality of blocks of the memory array; identifying respective categorizations of each of the plurality of sub-blocks; determining respective program pulse widths for each of the plurality of sub-blocks based on the respective categorizations; and causing a plurality of program voltage pulses having the respective program pulse widths to be applied to the one or more memory cells during the program operation. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the respective categorizations of each of the plurality of sub-blocks are based on physical locations of the plurality of sub-blocks within the one of the plurality of blocks. ### Claim 17 (depends on 15) The memory device of claim 15, wherein each respective categorization has a different corresponding program pulse width. ### Claim 18 (depends on 15) The memory device of claim 15, wherein each respective categorization comprises one of an outer-most sub-block disposed at an edge of one of the plurality of blocks, an inner-most sub-block disposed at a center of the one of the plurality of blocks, or a middle sub-block disposed between the outer-most sub-block and the inner-most sub-block of the one of the plurality of blocks. ### Claim 19 (depends on 15) The memory device of claim 15, wherein determining the respective program pulse widths for each of the plurality of sub-blocks comprises determining respective predefined periods, based on the respective categorizations, for which a corresponding program voltage pulse is to remain at a peak voltage level. ### Claim 20 (depends on 15) The memory device of claim 15, wherein the plurality of program voltage pulses having the respective program pulse widths to be applied to the one or more memory cells comprises loading respective values indicating the respective program pulse widths into an associated register.