Compute-in-memory circuits and methods for operating the same

A circuit, comprising:

• a first memory cell including a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, a second pass-gate transistor, a third pass-gate transistor, and a fourth pass-gate transistor;
• wherein the first and second pass-gate transistors of the first memory cell have their respective gate terminals connected to a first word line, and the third and fourth pass-gate transistors of the first memory cell have their respective gate terminals connected to a second word line;
• wherein the first word line is configured to receive a first logic state corresponding to a first data element being binarized, and the second word line is configured to receive a second logic state corresponding to the first data element being binarized;
• and
• wherein a first internal node of the first memory cell, accessible through one of its first or second pass-gate transistor, is configured to store a first logic state corresponding to a second data element being binarized, and a second internal node of the first memory cell, accessible through one of its third or fourth pass-gate transistor, is configured to store a second logic state corresponding to the second data element being binarized.

A method, comprising:

• providing a memory cell including a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, a second pass-gate transistor, a third pass-gate transistor, and a fourth pass-gate transistor, wherein the first and second pass-gate transistors have their gate terminals connected to a first word line, and the third and fourth pass-gate transistors have their gate terminals connected to a second word line, and wherein the first pass-gate transistor is coupled between a first internal node of the memory cell and a bit line, the second pass-gate transistor is coupled between a second internal node of the memory cell and a bit line bar, the third pass-gate transistor is coupled between the first internal node of the memory cell and the bit line bar, and the fourth pass-gate transistor is coupled between the second internal node of the memory cell and the bit line;
• storing, at the first internal node, a first data element with a first logic state;
• storing, at the second internal node, the first data element with a second logic state logically opposite to the first logic state, wherein one of the first or second logic state represents a first sign of the first data element being binarized;
• applying, on the first word line, a second data element with a third logic state;
• applying, on the second word line, the second data element with a fourth logic state logically opposite to the third logic state, wherein one of the third or fourth logic state represents a second sign of the second data element being binarized;
• identifying a voltage difference present between the bit line and the bit line bar;
• and
• providing a multiplication value of the first data element and the second data element, wherein the multiplication value, being binarized, has a third sign determined according to the first sign and the second sign.