# US 2026/0100220 A1 · Sram-based in-memory computing macro using analog computation scheme

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2026/0100220 A1
- Document ID: US20260100220A1
- Status: Published application
- Kind: A1
- Application number: 19/355,681
- Filed: 2025-10-10
- Published: 2026-04-09
- Earliest claimed: 2022-08-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Renzhi Liu; Hechen Wang; Richard Dorrance; Deepak Dasalukunte
- Web page: https://patentgrep.com/patent/US20260100220A1

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/412: using field-effect transistors only
- G11C 11/418: Address circuits
- G11C 11/419: Read-write [R-W] circuits
- G06F 2207/4814: Non-logic devices, e.g. operational amplifiers
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

An in-memory computing array comprising:
a bit line region;
a word line region;
an input and output region; and
a plurality of multiply-and-accumulate (MAC) computational units forming a MAC array, wherein:
a MAC computational unit includes a plurality of multi-bit multi-bank clusters wherein outputs of at least two multi-bit multi-bank clusters are electrically coupled to an output analog activation line;
a multi-bit multi-bank cluster includes a C-2C ladder electrically coupled to an input analog activation line and a plurality of single-bit multi-bank clusters stacked to form the multi-bit multi-bank cluster;
a single-bit multi-bank cluster comprising a part of the C-2C ladder and a plurality of static random access memory (SRAM) cells; and
one or more of the bit line region, the word line region, and the input and output region are located at grid locations associated with a compiled SRAM macro generated before an inclusion of the C-2C ladder.

### Claim 22 (depends on 21)

The in-memory computing array of claim 21, wherein a SRAM cell includes comprises a 9-transistor SRAM cell.

### Claim 23 (depends on 21)

The in-memory computing array of claim 21, wherein the plurality of single-bit multi-bank clusters are stacked in a first direction to form the multi-bit multi-bank cluster; and the plurality of multi-bit multi-bank clusters are stacked in a second direction orthogonal to the first direction.

### Claim 24 (depends on 23)

The in-memory computing array of claim 23, wherein the input analog activation line runs along the first direction.

### Claim 25 (depends on 23)

The in-memory computing array of claim 23, wherein the output analog activation line runs along the second direction.

### Claim 26 (depends on 23)

The in-memory computing array of claim 23, wherein the plurality of MAC computational units are stacked in the first direction.

### Claim 27 (depends on 21)

The in-memory computing array of claim 21, wherein the input analog activation line traverses across the word line region.

### Claim 28 (depends on 21)

The in-memory computing array of claim 21, wherein the output analog activation line traverses across the bit line region.

### Claim 29 (depends on 21)

The in-memory computing array of claim 21, wherein the in-memory computing array comprises a plurality of power lines located at further grid locations associated with the compiled SRAM macro generated before the inclusion of the C-2C ladder.

### Claim 30

One or more non-transitory computer readable storage media storing instructions, that when executed by a processor, cause a processor to:
receive a compiled static random access memory (SRAM) macro generated based on a size of an in-memory compute array, the compiled SRAM macro having a plurality of SRAM cell clusters, a bit line region, and a word line region;
form a single-bit multi-bank cell cluster from a SRAM cell cluster by:
removing a plurality of SRAM cells at a location of the SRAM cell cluster in the compiled SRAM macro;
adding a plurality of further SRAM cells at the location;
removing one or more yet further SRAM cells at a further location of the SRAM cell cluster of the compiled SRAM macro; and
adding a portion of a C-2C ladder at the further location;
form a multi-bit multi-bank cell cluster by duplicating the single-bit multi-bank cell cluster;
form a multiply-and-accumulate (MAC) computational unit by duplicating the multi-bit multi-bank cell cluster; and
form a MAC array by duplicating the MAC computational unit.

### Claim 31 (depends on 30)

The one or more non-transitory computer readable storage media of claim 30, wherein:
duplicating the single-bit multi-bank cell cluster comprises stacking a plurality of instances of the single-bit multi-bank cell cluster in a first direction; and
duplicating the multi-bit multi-bank cell cluster comprises stacking a plurality of instances of the multi-bit multi-bank cell cluster in a second direction that is orthogonal to the first direction.

### Claim 32 (depends on 30)

The one or more non-transitory computer readable storage media of claim 30, wherein the instructions further cause the processor to:
adding an input analog activation line to the C-2C ladder in a first direction; and
adding an output analog activation line to the C-2C ladder in a second direction that is orthogonal to the first direction.

### Claim 33 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein removing the plurality of SRAM cells comprises removing the plurality of SRAM cells located in a half of the SRAM cell cluster; and removing the one or more yet further SRAM cells comprises removing the one or more yet further SRAM cells in another half of the SRAM cell cluster.

### Claim 34 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein removing the plurality of SRAM cells comprises removing a first number of SRAM cells; and adding the plurality of further SRAM cells comprises adding a second number of SRAM cells, wherein the second number is less than the first number.

### Claim 35 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein the plurality of SRAM cells comprises a plurality of 6-transitor SRAM cells, and the plurality of further SRAM cells comprises a plurality of 9-transitor SRAM cells.

### Claim 36 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein adding the portion of the C-2C ladder comprises adding two capacitors and a control circuit at the further location.

### Claim 37 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein the instructions further cause the processor to:
add a plurality of input analog activation lines running in a first direction; and
add a plurality of output analog activation lines running in a second direction that is orthogonal to the first direction.

### Claim 38 (depends on 31)

The one or more non-transitory computer readable storage media of claim 31, wherein the instructions further cause the processor to:
form an expanded in-memory MAC computing array by duplicating the MAC array to form a two-dimensional grid of MAC arrays.

### Claim 39

A method for generating a static random access memory (SRAM) based in-memory computing macro, the method comprising:
receiving a compiled static random access memory (SRAM) macro generated based on a size of an in-memory compute array, the compiled SRAM macro having a plurality of SRAM cell clusters, a bit line region, and a word line region;
forming a single-bit multi-bank cell cluster from a SRAM cell cluster by:
removing a plurality of SRAM cells at a location of the SRAM cell cluster in the compiled SRAM macro;
adding a plurality of further SRAM cells at the location;
removing one or more yet further SRAM cells at a further location of the SRAM cell cluster of the compiled SRAM macro; and
adding a portion of a C-2C ladder at the further location;
forming a multi-bit multi-bank cell cluster by duplicating the single-bit multi-bank cell cluster;
forming a multiply-and-accumulate (MAC) computational unit by duplicating the multi-bit multi-bank cell cluster; and
forming a MAC array by duplicating the MAC computational unit.

### Claim 40 (depends on 39)

The method of claim 39, wherein:
duplicating the single-bit multi-bank cell cluster comprises stacking a plurality of instances of the single-bit multi-bank cell cluster in a first direction; and
duplicating the multi-bit multi-bank cell cluster comprises stacking a plurality of instances of the multi-bit multi-bank cell cluster in a second direction that is orthogonal to the first direction.