# US 2026/0100219 A1 · Write duty cycle calibration on a memory device

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- Number: US 2026/0100219 A1
- Document ID: US20260100219A1
- Status: Published application
- Kind: A1
- Application number: 19/406,043
- Filed: 2025-12-02
- Published: 2026-04-09
- Earliest claimed: 2022-08-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Luigi Pilolli; Guan Wang; Rosario D’Esposito; Andrew Proescholdt; Lucia Botticchio; Luca Di Loreto
- Web page: https://patentgrep.com/patent/US20260100219A1

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4099: Dummy cell treatment; Reference voltage generators
- G11C 16/10: Programming or data input circuits
- G11C 16/32: Timing circuits
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device including an array of memory cells and a circuit disposed within the memory device to compare a voltage level associated with a selected digital data input signal corresponding to a write operation associated with a set of memory cells of the array of memory cells to a reference voltage level to generate a comparison result. The memory device further includes control logic operatively coupled to the circuit, the control logic to identify, based on the comparison result, a duty cycle distortion level associated with the selected digital data input signal; and generate, based on the duty cycle distortion level, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal.

## Claims

### Claim 1

A memory device comprising:
an array of memory cells;
a circuit disposed within the memory device to compare a voltage level associated with a selected digital data input signal corresponding to a write operation associated with a set of memory cells of the array of memory cells to a reference voltage level to generate a comparison result; and
control logic operatively coupled to the circuit, the control logic to:
identify, based on the comparison result, a duty cycle distortion level associated with the selected digital data input signal; and
generate, based on the duty cycle distortion level, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the comparison result comprises one of: a first result indicating the voltage level is greater than the reference voltage level, a second result indicating the voltage level is less than the reference voltage level.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising a low pass filter configured to receive the selected digital data input signal and generate the voltage level associated with the selected digital data input signal.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising a duty cycle adjustment component operatively coupled to the control logic, the duty cycle adjustment component configured to receive the command from the control logic and adjust the duty cycle associated with the selected digital data input signal based on the code.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the duty cycle adjustment component comprises a set of logic gates configured to be controlled based on the code to adjust a timing of the selected digital data input signal.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein the duty cycle adjustment component is configured to adjust the duty cycle by one of: decreasing a width of a high pulse of the selected digital data input signal or increasing the width of the high pulse of the selected digital data input signal.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the control logic is configured to receive a duty cycle calibration command from a memory sub-system controller, and wherein the duty cycle calibration command identifies the selected digital data input signal from a plurality of digital data input signals associated with the memory device.

### Claim 8

A memory device comprising:
an array of memory cells;
a first circuit to generate a voltage level associated with a selected digital data input signal of a set of digital data input signals, wherein the selected digital data input signal corresponds to a write operation associated with one or more memory cells of the array of memory cells;
a second circuit to compare the voltage level to a reference voltage level to generate a comparison result; and
control logic operatively coupled to the second circuit, the control logic to:
receive a duty cycle calibration command from a memory sub-system controller, the duty cycle calibration command identifying the selected digital data input signal from the set of digital data input signals; and
generate, based on the comparison result, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal.

### Claim 9 (depends on 8)

The memory device of claim 8, further comprising a third circuit operatively coupled to the control logic, the third circuit to:
receive the code from the control logic; and
adjust the duty cycle associated with the selected digital data input signal based on the code.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the third circuit comprises a set of logic gates configured to be controlled based on the code to adjust a timing of the selected digital data input signal.

### Claim 11 (depends on 9)

The memory device of claim 9, wherein the third circuit is configured to adjust the duty cycle by one of: decreasing a width of a high pulse of the selected digital data input signal or increasing the width of the high pulse of the selected digital data input signal.

### Claim 12 (depends on 8)

The memory device of claim 8, wherein the first circuit comprises a low pass filter configured to receive the selected digital data input signal and generate the voltage level associated with the selected digital data input signal.

### Claim 13 (depends on 8)

The memory device of claim 8, wherein the second circuit comprises a comparator circuit configured to generate the comparison result indicating one of: the voltage level is greater than the reference voltage level or the voltage level is less than the reference voltage level.

### Claim 14 (depends on 8)

The memory device of claim 8, wherein the control logic is further configured to store the code in a read only memory location associated with the selected digital data input signal.

### Claim 15

A memory device comprising:
an array of memory cells;
control logic operatively coupled to the array of memory cells, the control logic to:
identify a duty cycle distortion level associated with a selected digital data input signal of a plurality of digital data input signals; and
generate, based on the duty cycle distortion level, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal; and
a duty cycle adjustment component operatively coupled to the control logic, the duty cycle adjustment component configured to:
receive the command from the control logic; and
adjust the duty cycle associated with the selected digital data input signal based on the code.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the duty cycle distortion level is identified based on a result of a comparison of a voltage level associated with a selected digital data input signal corresponding to a write operation associated with a set of memory cells of the array of memory cells to a reference voltage level.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the result indicates one of the voltage level is greater than the reference voltage level or the voltage level is less than the reference voltage level.

### Claim 18 (depends on 16)

The memory device of claim 16, further comprising a low pass filter configured to receive the selected digital data input signal and generate the voltage level associated with the selected digital data input signal.

### Claim 19 (depends on 15)

The memory device of claim 15, wherein the duty cycle adjustment component comprises a set of logic gates configured to be controlled based on the code to adjust a timing of the selected digital data input signal.

### Claim 20 (depends on 15)

The memory device of claim 15, wherein the control logic receives a duty cycle calibration command from a memory sub-system controller, and wherein the duty cycle calibration command identifies the selected digital data input signal from a plurality of digital data input signals associated with the memory device.