# US 2026/0100218 A1 · Apparatus for data read timing calibration in stacked memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100218 A1 - Document ID: US20260100218A1 - Status: Published application - Kind: A1 - Application number: 19/347,543 - Filed: 2025-10-01 - Published: 2026-04-09 - Earliest claimed: 2024-10-08 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Jaeil Kim; Nicole Kang; Vijayakrishna Vankayala; Jason M. Brown - Web page: https://patentgrep.com/patent/US20260100218A1 ## CPC - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the disclosure provide an apparatus comprising a plurality of through-silicon vias (TSVs), a plurality of core dies, and a calibration circuit. The core dies are stacked with one another, and each core die outputs read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal. The calibration circuit compares data read timings of the core dies to determine a slowest core die, and adds a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die. ## Claims ### Claim 1 An apparatus, comprising: a plurality of through-silicon vias (TSVs); a plurality of core dies stacked with one another, each core die configured to output read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal; and a calibration circuit configured to: compare data read timings of the core dies to determine a slowest core die; and add a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein the calibration circuit compares state transitions of the read data of the respective core dies to compare the data read timings. ### Claim 3 (depends on 2) The apparatus according to claim 2, wherein the state transitions include a transition from a first state to a second state, and the first state is one of a high state and a low state, and the second state is another of the high state and the low state. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein the calibration circuit comprises one or more flip-flop circuits configured to receive the read data from the respective core dies as data signals and as clock signals and output a calibration control signal to keep the read timing of the slowest core die uncalibrated. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein the calibration circuit comprises: a plurality of first flip-flop circuits configured to receive the read data from corresponding core dies of the plurality of core dies as first data signals, receive the read data from at least one core die selected from the plurality of core dies as a first clock signal, and output first calibration control signals; and a second flip-flop circuit configured to receive the first calibration control signals as a second data signal, receive a second clock signal, and output a second calibration control signal to indicate the slowest core die. ### Claim 6 (depends on 5) The apparatus according to claim 5, wherein if all of the first calibration control signals output from the first flip-flop circuits are in a high state, the second calibration control signal from the second flip-flop circuit indicates that the selected core die is the slowest core die. ### Claim 7 (depends on 1) The apparatus according to claim 1, wherein the at least one of the core dies other than the slowest core die is a calibration-target core die, and the calibration circuit comprises: a phase detecting circuit configured to receive the read data from the slowest core die as a data signal, receive the read data from the calibration-target core die as a clock signal, and output a phase detection result; and a delay adding circuit configured to add the delay to the read enable signal of the calibration-target core die in response to the phase detection result. ### Claim 8 (depends on 7) The apparatus according to claim 7, wherein the delay adding circuit calibrates an amount of the delay in response to a delay amount control signal, the delay amount control signal changes a value thereof at every calibration timing and controls the amount of the delay. ### Claim 9 (depends on 7) The apparatus according to claim 7, wherein the calibration timing is repeatedly set in response to a clock signal generated in response to a read command for calibration until the read enable signal is disabled. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein the plurality of core dies each comprise a data output circuit coupled to at least one of the assigned TSVs to output the read data in response to the read enable signal. ### Claim 11 (depends on 1) The apparatus according to claim 1, wherein a bottom core die of the stacked core dies is a master chip configured to receive a read command for calibration from external devices, and upper core dies are slave chips configured to receive the read command from the master chip through the TSVs, the read command triggers the read enable signal, and the read command for calibration is used to generate the read enable signal. ### Claim 12 (depends on 1) The apparatus according to claim 1, wherein a bottom core die of the stacked core dies is an interface die configured to receive a read command for calibration from external devices, and upper core dies are configured to receive the read command from the master chip through the TSVs, and the read command is used to generate the read enable signal. ### Claim 13 An apparatus, comprising: a plurality of through-silicon vias (TSVs); a plurality of core dies stacked with one another, each core die configured to output read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal; and a calibration circuit configured to: compare data read timings of the core dies to determine a slowest core die; and add a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die, wherein the calibration circuit includes: a plurality of first flip-flop circuits configured to receive the read data from corresponding core dies of the plurality of core dies as first data signals, receive the read data from at least one core die selected from the plurality of core dies as a first clock signal, and output first calibration control signals; and a second flip-flop circuit configured to receive the first calibration control signals as a second data signal, receive a second clock signal, and output a second calibration control signal to indicate the slowest core die, and if all of the first calibration control signals output from the first flip-flop circuits are in a high state, the second calibration control signal from the second flip-flop circuit indicates that the selected core die is the slowest core die. ### Claim 14 (depends on 13) The apparatus according to claim 13, wherein the calibration circuit compares state transitions of the read data of the respective core dies to compare the data read timings, the state transitions include a transition from a first state to a second state, and the first state is one of a high state and a low state, and the second state is another of the high state and the low state. ### Claim 15 (depends on 13) The apparatus according to claim 13, wherein the at least one of the core dies other than the slowest core die is a calibration-target core die, and the calibration circuit comprises: a phase detecting circuit configured to receive the read data from the slowest core die as a data signal, receive the read data from the calibration-target core die as a clock signal, and output a phase detection result; and a delay adding circuit configured to add a delay to the read enable signal of the calibration-target core die in response to the phase detection result. ### Claim 16 (depends on 15) The apparatus according to claim 15, wherein the delay adding circuit calibrates an amount the delay in response to a delay amount control signal, the delay amount control signal changes a value thereof at every calibration timing and controls the amount of the delay. ### Claim 17 An apparatus, comprising: a plurality of through-silicon vias (TSVs); a plurality of core dies stacked with one another, each core die configured to output read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal; and a calibration circuit configured to: compare data read timings of the core dies to determine a slowest core die; and add a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die, wherein the at least one of the core dies other than the slowest core die is a calibration-target core die, and the calibration circuit includes: a phase detecting circuit configured to receive the read data from the slowest core die as a data signal, receive the read data from the calibration-target core die as a clock signal, and output a phase detection result; and a delay adding circuit configured to calibrate an amount of the delay in response to the phase detection result and a delay amount control signal, the delay amount control signal changing a value thereof at every calibration timing, and to add the delay of the calibrated amount to the read enable signal of the calibration-target core die. ### Claim 18 (depends on 17) The apparatus according to claim 17, wherein the calibration timing is repeatedly set in response to a clock signal generated in response to a read command for calibration until the read enable signal is disabled. ### Claim 19 (depends on 17) The apparatus according to claim 17, wherein the calibration circuit compares state transitions of the read data of the respective core dies to compare the data read timings, the state transitions include a transition from a first state to a second state, and the first state is one of a high state and a low state, and the second state is another of the high state and the low state. ### Claim 20 (depends on 17) The apparatus according to claim 17, wherein the calibration circuit comprises: a plurality of first flip-flop circuits configured to receive the read data from corresponding core dies of the plurality of core dies as first data signals, receive the read data from at least one core die selected from the plurality of core dies as a first clock signal, and output first calibration control signals; and a second flip-flop circuit configured to receive the first calibration control signals as a second data signal, receive a second clock signal, and output a second calibration control signal to indicate the slowest core die, and if all of the first calibration control signals output from the first flip-flop circuits are in a high state, the second calibration control signal from the second flip-flop circuit indicates that the selected core die is the slowest core die.