# US 2026/0100209 A1 · Dummy Wordline Driver Circuitry and Methods

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- Number: US 2026/0100209 A1
- Document ID: US20260100209A1
- Status: Published application
- Kind: A1
- Application number: 18/910,457
- Filed: 2024-10-09
- Published: 2026-04-09
- Earliest claimed: 2024-10-09
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Disha Singh; Rajiv Kumar Sisodia; Prashantkumar Jayantilal Vaghasia
- Web page: https://patentgrep.com/patent/US20260100209A1

## CPC

- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A circuit to precharge a dummy wordline includes a first branch comprising first and second PMOS devices; and a second branch comprising a single PMOS device. Also, in response to a power supply transition, the second branch can be configured to precharge the dummy wordline through the single PMOS device. Also, a method to precharge a dummy wordline includes: precharging, by a first branch of a circuit, a dummy wordline, and in response to a power supply transition, precharging the dummy wordline through a single PMOS device of a second branch of the circuit.

## Claims

### Claim 1

A circuit comprising:
a first branch comprising first and second PMOS devices; and
a second branch comprising a single PMOS device, wherein:
in response to a power supply transition, the second branch is configured to precharge a dummy wordline (DWL) through the single PMOS device.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein
the power supply transition is based on an activation of the first PMOS device, and
the first PMOS device is configured for activation upon receiving a derivation of an inverted clock signal or a delayed derivation of the inverted clock signal.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein during the power supply transition, the single PMOS device of the second branch is configured to receive an inverted clock signalconfigured to core operating voltage.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the power supply transition occurs independent from one or more feedback signals based on the DWL.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein:
the first branch comprises a supply voltage power rail and is configured to peripheral operating voltage, and the supply voltage power rail is coupled to the first and second PMOS devices in series, and wherein:
the second branch comprises a core voltage power rail and is configured to core operating voltage, and the core voltage power rail is coupled to the single PMOS device of the second branch.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein:
the second PMOS device of the first branch is configured for activation upon receiving an inverted clock signal, and
upon activation of the second PMOS device, the circuit is configured to precharge the DWL through the first branch prior to the power supply transition.

### Claim 7 (depends on 1)

The circuit of claim 1, further comprising:
an NMOS device coupled to the first and second branches, wherein:
the NMOS is coupled to the second PMOS device of the first circuit branch, and
the NMOS is coupled to the single PMOS device of the second circuit branch.

### Claim 8 (depends on 1)

The circuit of claim 1, further comprising:
a common mode level shifter (CMLS) coupled to the circuit, wherein:
the CMLS is configured to generate an inverted clock signal configured to core operating voltage based on a derivation of the inverted clock signal or a delayed derivation of the inverted clock signal;
the CMLS is configured to transmit the inverted clock signal configured to the core operating voltage to the single PMOS device of the second branch.

### Claim 9 (depends on 1)

The circuit of claim 1, further comprising:
an inverter, wherein:
the inverter is coupled to the circuit; and
the inverter is configured to generate a derivation of an inverted clock signal based on the inverted clock signal.

### Claim 10 (depends on 1)

The circuit of claim 1, further comprising:
first and second inverters, wherein:
the first and second inverters are coupled to the circuit; and
the first and second inverters are configured to generate a delayed derivation of an inverted clock signal based on a derivation of the inverted clock signal.

### Claim 11 (depends on 1)

The circuit of claim 1, further comprising:
a delay generation circuit, wherein:
the delay generation circuit is coupled to the circuit; and
the delay generation circuit is configured to transmit a derivation of an inverted clock signal or a delayed derivation of the inverted clock signal to the circuit based on an edge mode average (EMA) selection.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein a transmission of the delayed derivation of the inverted clock signal, by the delay generation circuit, is configured to delay the activation of the single PMOS device of the second branch.

### Claim 13 (depends on 1)

The circuit of claim 1, wherein the first branch comprises:
a third PMOS device, wherein:
the first and second devices of the first branch are configured to peripheral operating voltage,
the third PMOS device is coupled in series with the first and second PMOS devices,
the third PMOS device is configured to receive a derivation of an inverted clock signal configured to core operating voltage, and
the third PMOS device is configured to be deactivated when the peripheral operating voltage is greater than the core operating voltage on the first branch.

### Claim 14

A method comprising:
precharging, by a first branch of a circuit, a dummy wordline (DWL); and
in response to a power supply transition, precharging the DWL through a single PMOS device of a second branch of the circuit.

### Claim 15 (depends on 14)

The method of claim 14, wherein the power supply transition occurs independent from one or more feedback signals based on the DWL.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
the power supply transition is based on an activation of a first PMOS device, and
the first PMOS device is configured for activation upon receiving a derivation of an inverted clock signal or a delayed derivation of the inverted clock signal.

### Claim 17 (depends on 14)

The method of claim 14, wherein:
the power supply transition corresponds to a transition delay, and
the transition delay corresponds to a difference in duration between an inverted clock signal configured to peripheral operating voltage and an inverted clock signal configured to core operating voltage.

### Claim 18 (depends on 14)

The method of claim 14, wherein precharging the DWL by the first branch comprises:
in response to a second PMOS device of the first branch receiving an inverted clock signal, activating the second PMOS device of the first branch; and
upon the activation of the second PMOS device of the first branch, precharging the DWL through the first branch prior to the power supply transition.

### Claim 19 (depends on 14)

The method of claim 14, wherein precharging the DWL by the single PMOS device of the second branch comprises:
in response to the single PMOS device receiving an inverted clock signal configured to core operating voltage, activating the single PMOS device of the second branch; and
upon the activation of the single PMOS device of the second branch, precharging the DWL through the second branch after the power supply transition.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
receiving, by a third PMOS device of the first branch, a derivation of an inverted clock signal configured to core operating voltage, wherein:
the third PMOS device is configured to be deactivated when peripheral operating voltage is greater than the core operating voltage on the first branch.