# US 2026/0100206 A1 · Semiconductor memory devices with embedded power structure and methods of manufacturing thereof

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- Number: US 2026/0100206 A1
- Document ID: US20260100206A1
- Status: Published application
- Kind: A1
- Application number: 19/049,338
- Filed: 2025-02-10
- Published: 2026-04-09
- Earliest claimed: 2024-10-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ting-Yun Wu; Lu Yang; Szuya Liao; Jui-Lin Chen; Kian-Long Lim; Ping-Wei Wang; Yung-Ting Chang
- Web page: https://patentgrep.com/patent/US20260100206A1

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 89/10: Integrated device layouts
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/2565: {wherein the source or drain regions are on a top side of the semiconductor bodies and the recessed source or drain electrodes are on a bottom side of the semiconductor bodies}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes a substrate having a first side and a second side; a first transistor and a second transistor formed in a first level on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second level on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, the first and second interconnect structures each configured to carry a supply voltage, and the third and fourth interconnect structures each configured to carry a ground voltage; and a power structure vertically extending through the first and second levels, and configured to electrically couple a source/drain terminal of the third transistor and a source/drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

## Claims

### Claim 1

A device, comprising:
a substrate having a first side and a second side opposite to each other;
a first transistor and a second transistor in a first level on the first side of the substrate, the first and second transistors having a first conductivity;
a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor in a second level on the first side of the substrate and over the first level, the third to sixth transistors having a second conductivity;
a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side of the substrate, wherein the first and second interconnect structures are each configured to carry a supply voltage, and the third and fourth interconnect structures are each configured to carry a ground voltage; and
a power structure vertically extending through the first and second levels, and configured to electrically couple a source/drain terminal of the third transistor and a source/drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively;
wherein, when viewed from a top of the device, the power structure is interposed between the fifth transistor and the fourth transistor along a first lateral direction, and between the third transistor and the sixth transistor along the first lateral direction.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a first dummy transistor disposed next to the first transistor along a second lateral direction perpendicular to the first lateral direction, and having a source/drain terminal replaced with a first isolation structure; and
a second dummy transistor disposed next to the second transistor along the second lateral direction, and having a source/drain terminal replaced with a second isolation structure.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first dummy transistor and second dummy transistor are each formed with the first conductivity.

### Claim 4 (depends on 2)

The device of claim 2, further comprising:
a first contact structure electrically connected to the source/drain terminal of the third transistor;
a second contact structure electrically connected to the source/drain terminal of the fourth transistor;
a third contact structure vertically disposed below the first isolation structure, and electrically connected to the third interconnect structure; and
a fourth contact structure vertically disposed below the second isolation structure, and electrically connected to the fourth interconnect structure.

### Claim 5 (depends on 4)

The device of claim 4, wherein the power structure is formed as a one-piece wall structure, the one-piece wall structure being configured to connect the first and second contact structures to the third and fourth contact structures.

### Claim 6 (depends on 4)

The device of claim 4, wherein the power structure is formed as a first via structure and a second via structure, the first via structure being configured to connect the first contact structure to the third contact structure, and the second via structure being configured to connect the second contact structure to the fourth contact structure.

### Claim 7 (depends on 1)

The device of claim 1, wherein each of the first to fourth interconnect structures extends along a second lateral direction perpendicular to the first lateral direction.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first interconnect structure and the third interconnect structure are aligned along the second lateral direction, and the second interconnect structure and the fourth interconnect structure are aligned along the second lateral direction.

### Claim 9 (depends on 7)

The device of claim 7, wherein the first interconnect structure and the third interconnect structure are disposed opposite the first transistor from the power structure along the first lateral direction, and the second interconnect structure and the fourth interconnect structure are disposed opposite the second transistor from the power structure along the first lateral direction.

### Claim 10 (depends on 1)

The device of claim 1, wherein the first to sixth transistors operatively form a Static Random Access Memory (SRAM) cell.

### Claim 11

A semiconductor device, comprising:
a first active region formed at a first level on a first side of a substrate and extending along a first lateral direction;
a second active region formed at the first level and extending along the first lateral direction;
a first gate structure formed at the first level, extending in a second lateral direction, and traversing the first and second active regions;
a second gate structure formed at the first level, extending in the second lateral direction, and traversing the first and second active regions;
a third active region formed at a second level over the first level on the first side, extending in the first lateral direction, and vertically above and aligned with the first active region;
a fourth active region formed at the second level, extending in the first lateral direction, and vertically above and aligned with the second active region;
a third gate structure formed at the second level, extending in the second lateral direction, and vertically above and aligned with the third active region;
a fourth gate structure formed at the second level, extending in the second lateral direction, and vertically above and aligned with the fourth active region; and
a power structure vertically extending from the first level to the second level, interposed between the first active region and the second active region along the second lateral direction, and interposed between the third active region and the fourth active region along the second lateral direction;
wherein the first active region and the second gate structure operatively form a first transistor of a memory cell that has a first conductivity, the second active region and the first gate structure operatively form a second transistor of the memory cell that has the first conductivity, the third active region and the third gate structure operatively form a third transistor of the memory cell that have a second conductivity, the third active region and the fourth gate structure operatively form a fourth transistor of the memory cell that have the second conductivity, the fourth active region and the third gate structure operatively form a fifth transistor of the memory cell that have the second conductivity, and the fourth active region and the fourth gate structure operatively form a sixth transistor of the memory cell that have the second conductivity.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the memory cell is a Static Random Access Memory (SRAM) cell.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein
the first active region and the first gate structure operatively form a first dummy first transistor that has a source/drain terminal replaced with a first isolation structure; and
the second active region and the second gate structure operatively form a second dummy first transistor that has a source/drain terminal replaced with a second isolation structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising:
a first contact structure having at least a portion vertically disposed over and electrically connected to a source/drain terminal of the fourth transistor;
a second contact structure having at least a portion vertically disposed over and electrically connected to a source/drain terminal of the fifth transistor;
a third contact structure vertically disposed below the first isolation structure; and
a fourth contact structure vertically disposed below the second isolation structure.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising:
a first interconnect structure formed on a second side of the substrate, extending along the first lateral direction, and configured to carry a ground voltage, the third contact structure being coupled to the first interconnect structure; and
a second interconnect structure formed on the second side of the substrate, extending along the first lateral direction, and configured to carry the ground voltage, the fourth contact structure being coupled to the second interconnect structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the power structure is formed as a one-piece wall structure, the one-piece wall structure being configured to connect the first and second contact structures to the third and fourth contact structures.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the power structure is formed as a first via structure and a second via structure, the first via structure being configured to connect the first contact structure to the third contact structure, and the second via structure being configured to connect the second contact structure to the fourth contact structure.

### Claim 18

A method for forming a memory device, comprising:
forming, at a first level on a first side of a substrate, a first active region extending along a first lateral direction;
forming, at the first level, a second active region extending along the first lateral direction;
forming, at the first level, a first gate structure extending along a second lateral direction and traversing the first and second active regions;
forming, at the first level, a second gate structure extending along the second lateral direction and traversing the first and second active regions;
forming, at a second level over the first level on the first side, a third active region extending in the first lateral direction;
forming, at the second level, a fourth active region extending along the first lateral direction;
forming, at the second level, a third gate structure extending along the second lateral direction;
forming, at the second level, a fourth gate structure extending along the second lateral direction; and
forming a power structure vertically extending from the first level to the second level, interposed between the first active region and the second active region along the second lateral direction, and interposed between the third active region and the fourth active region along the second lateral direction;
wherein the first active region and the second gate structure operatively form a first transistor of a memory cell that has a first conductivity, the second active region and the first gate structure operatively form a second transistor of the memory cell that has the first conductivity, the third active region and the third gate structure operatively form a third transistor of the memory cell that have a second conductivity, the third active region and the fourth gate structure operatively form a fourth transistor of the memory cell that have the second conductivity, the fourth active region and the third gate structure operatively form a fifth transistor of the memory cell that have the second conductivity, and the fourth active region and the fourth gate structure operatively form a sixth transistor of the memory cell that have the second conductivity.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming, on a second side of the substrate, a first interconnect structure configured to carry a ground voltage; and
forming, on the second side of the substrate, a second interconnect structure configured to carry the ground voltage;
wherein the power structure is configured to electrically couple respective source/drain terminals of the fourth and fifth transistors to the ground voltage.

### Claim 20 (depends on 18)

The method of claim 18, wherein the power structure is formed as a one-piece wall structure or a pair of via structures.