# US 2026/0100166 A1 · Display device

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- Number: US 2026/0100166 A1
- Document ID: US20260100166A1
- Status: Published application
- Kind: A1
- Application number: 19/272,345
- Filed: 2025-07-17
- Published: 2026-04-09
- Earliest claimed: 2024-10-07
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Ki Tae KWON; Yong Won JO; Jong Wook JANG
- Web page: https://patentgrep.com/patent/US20260100166A1

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3677: {suitable for active matrices only}
- G09G 2230/00: Details of flat display driving waveforms
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0871: with level shifting
- G09G 2310/0205: Simultaneous scanning of several lines in flat panels
- G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged. A data driver is configured to output data voltages to the plurality of data lines. A gate driver arranged in the pixel array and configured to output gate signals to the plurality of gate lines. A level shifter is configured to generate first and second clock signals for the gate driver. The gate driver includes a first gate driver arranged on odd-numbered column lines and configured to receive the first clock signal. The gate driver also includes a second gate driver arranged on even-numbered column lines and configured to receive the second clock signal.

## Claims

### Claim 1

A display device comprising:
a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged;
a data driver configured to output data voltages to the plurality of data lines;
a gate driver arranged in the pixel array and configured to output gate signals to the plurality of gate lines; and
a level shifter configured to generate first and second clock signals for the gate driver,
wherein the gate driver comprises:
a first gate driver arranged on odd-numbered column lines and configured to receive the first clock signal; and
a second gate driver arranged on even-numbered column lines and configured to receive the second clock signal.

### Claim 2 (depends on 1)

The display device of claim 1, further comprising:
a first clock line configured to apply the first clock signal to the first gate driver; and
a second clock line configured to apply the second clock signal to the second gate driver.

### Claim 3 (depends on 2)

The display device of claim 2, wherein the first gate driver is arranged on odd-numbered column lines and odd-numbered row lines, and
the second gate driver is arranged on even-numbered column lines and even-numbered row lines.

### Claim 4 (depends on 3)

The display device of claim 3, wherein the first clock signal and the second clock signal have different phases.

### Claim 5 (depends on 4)

The display device of claim 4, wherein each of the first clock signal and the second clock signal has a pulse width of 2H.

### Claim 6 (depends on 2)

The display device of claim 2, wherein the first gate driver is arranged on all row lines of odd-numbered column lines, and
the second gate driver is arranged on all row lines of even-numbered column lines.

### Claim 7 (depends on 6)

The display device of claim 6, wherein the first clock signal and the second clock signal have the same phase.

### Claim 8 (depends on 7)

The display device of claim 7, wherein each of the first clock signal and the second clock signal has a pulse width of 1H.

### Claim 9

A display device comprising:
a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged;
a data driver configured to output data voltages to the plurality of data lines;
a scan driver arranged in the pixel array and configured to output scan signals to the plurality of gate lines;
an EM driver arranged in the pixel array and configured to output emission control signals to the plurality of gate lines; and
a level shifter configured to generate clock signals for the scan driver and the EM driver,
wherein the EM driver comprises:
a first EM driver arranged on odd-numbered column lines and configured to receive a first-phase clock signal; and
a second EM driver arranged on even-numbered column lines and configured to receive a second-phase clock signal.

### Claim 10 (depends on 9)

The display device of claim 9, further comprising:
a first clock line configured to apply the first-phase clock signal to the first EM driver; and
a second clock line configured to apply the second-phase clock signal to the second EM driver.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the first EM driver is arranged on odd-numbered column lines and odd-numbered row lines, and
the second EM driver is arranged on even-numbered column lines and even-numbered row lines.

### Claim 12 (depends on 11)

The display device of claim 11, wherein the first-phase clock signal and the second-phase clock signal are four-phase clock signals.

### Claim 13 (depends on 12)

The display device of claim 12, wherein each of the first-phase clock signal and the second-phase clock signal has a pulse width of 2H.

### Claim 14 (depends on 10)

The display device of claim 10, wherein the first EM driver is arranged on all row lines of odd-numbered column lines, and
the second EM driver is arranged on all row lines of even-numbered column lines.

### Claim 15 (depends on 14)

The display device of claim 14, wherein the first-phase clock signal and the second-phase clock signal are two-phase clock signals.

### Claim 16 (depends on 15)

The display device of claim 15, wherein each of the first-phase clock signal and the second-phase clock signal has a pulse width of 1H.

### Claim 17 (depends on 9)

The display device of claim 9, wherein the EM driver comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, and
a first capacitor, a second capacitor, and a third capacitor,
wherein the first transistor includes a gate electrode to which a second clock signal is applied, a first electrode to which a start signal is applied, and a second electrode connected to a first node;
the second transistor includes a gate electrode to which a first clock signal is applied, a first electrode connected to the first node, and a second electrode connected to a second node;
the third transistor includes a gate electrode connected to a third node, a first electrode connected to the second node, and a second electrode connected to a first power line to which a high-potential voltage is applied;
the fourth transistor includes a gate electrode connected to a second power line to which a low-potential voltage is applied, a first electrode connected to the first node, and a second electrode connected to a first control node;
the fifth transistor includes a gate electrode to which the second clock signal is applied, a first electrode connected to the second power line, and a second electrode connected to the third node;
the sixth transistor includes a gate electrode connected to the first node, a first electrode to which the second clock signal is applied, and a second electrode connected to the third node;
the seventh transistor includes a gate electrode connected to the second power line, a first electrode connected to the third node, and a second electrode connected to a fourth node;
the eighth transistor includes a gate electrode connected to the fourth node, a first electrode to which the first clock signal is applied, and a second electrode connected to a fifth node;
the ninth transistor includes a gate electrode to which the first clock signal is applied, a first electrode connected to the fifth node, and a second electrode connected to a second control node;
the tenth transistor includes a gate electrode connected to the first node, a first electrode connected to the second control node, and a second electrode connected to the first power line;
the eleventh transistor includes a gate electrode connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to a sixth node;
the twelfth transistor includes a gate electrode connected to the first control node, a first electrode connected to the second power line, and a second electrode connected to an output node;
the thirteenth transistor includes a gate electrode connected to the second control node, a first electrode connected to the output node, and a second electrode connected to the first power line;
the first capacitor is connected between a gate electrode and a source electrode of the eighth transistor;
the second capacitor is connected between a gate electrode of the twelfth transistor and a source electrode of the eleventh transistor; and
the third capacitor is connected between a gate electrode and a source electrode of the thirteenth transistor.