# US 2026/0100151 A1 · Device and method for supporting image data shifting in a display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100151 A1 - Document ID: US20260100151A1 - Status: Published application - Kind: A1 - Application number: 19/329,556 - Filed: 2025-09-15 - Published: 2026-04-09 - Earliest claimed: 2024-04-03 - Assignees: Sapien Semiconductors Inc. - Applicants: Sapien Semiconductors Inc. - Inventors: Jin Woong JANG; Jinhang LEE - Web page: https://patentgrep.com/patent/US20260100151A1 ## CPC - G09G 3/007: {Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels} - G06F 3/01: Input arrangements or combined input and output arrangements for interaction between user and computer (G06F3/16 takes precedence) - G09G 3/00: Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 5/00: Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2320/0261: in the context of movement of objects on the screen or movement of the observer relative to the screen - G09G 2340/0464: Positioning - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed are a device and a method for supporting image data movement within a display. The display device may include a controller configured to control data writing, driving of a light-emitting element, and data movement, and a plurality of pixels each including a pixel-embedded memory configured to store image data represented by a multi-bit value. Each of the plurality of pixels may be configured to store image data in the pixel-embedded memory during a data write time interval and shift the image data stored in the pixel-embedded memory to one of upper, lower, left, or right adjacent pixels based on a control signal input from the controller during a data movement time interval. ## Claims ### Claim 1 A display device comprising: a controller configured to control data writing, driving of a light-emitting element, and data movement; and a plurality of pixels each including a pixel-embedded memory configured to store image data represented by a multi-bit value, wherein each of the plurality of pixels is configured to store the image data in the pixel-embedded memory during a data write time interval, and shift the image data stored in the pixel-embedded memory to one of upper, lower, left, or right adjacent pixels based on a control signal input from the controller during a data movement time interval. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the pixel-embedded memory comprises: a first dummy shift register configured to retrieve 1-bit data stored in a pixel-embedded memory of an adjacent pixel; n-bit shift registers configured to store n-bit image data; and a second dummy shift register configured to retrieve 1-bit data stored in the n-bit shift registers. ### Claim 3 (depends on 2) The display device according to claim 2, wherein the first dummy shift register operates to retrieve 1-bit data stored in the pixel-embedded memory of the adjacent pixel at a first clock of the data movement time interval, the second dummy shift register operates to retrieve 1-bit data stored in the n-bit shift registers at a second clock of the data movement time interval, and each of the n-bit shift registers is configured to shift 1-bit data starting from a third clock of the data movement time interval. ### Claim 4 (depends on 2) The display device according to claim 2, wherein the first dummy shift register and the second dummy shift register include a reset switch for resetting the registers after the movement of the image data. ### Claim 5 (depends on 2) The display device according to claim 2, wherein image data shift between left and right adjacent pixels connected to the same column line is performed during n+1 line times. ### Claim 6 (depends on 5) The display device according to claim 5, wherein image data shift between upper and lower adjacent pixels includes image data shift from a first pixel of a first column line to a second pixel of a second column line, the first pixel performs bit-wise shift in the order of a first dummy shift register, a second dummy shift register, and the n-bit shift registers during a clock cycle of the first column line, and the second pixel performs bit-wise shift in the order of a first dummy shift register, a second dummy shift register, and the n-bit shift registers during a clock cycle of the second line delayed by one line time compared to the clock cycle of the first column line. ### Claim 7 A pixel of a display device comprising: a light-emitting element; and a pixel circuit connected to the light-emitting element, wherein the pixel circuit comprises: a path controller configured to select a connection path with an adjacent pixel based on a control signal input from a controller; and a pixel-embedded memory configured to store image data represented by a multi-bit value during a data write time interval, and shift the image data through the connection path with the adjacent pixel during a data movement time interval. ### Claim 8 (depends on 7) The pixel of the display device according to claim 7, wherein the path controller comprises: a first path controller configured to select a reception path of the image data based on a type of the control signal; and a second path controller configured to select an output path of the image data based on the type of the control signal. ### Claim 9 (depends on 8) The pixel of the display device according to claim 8, wherein the type of the control signal comprises: an up control signal (M_UP) for moving the image data to an upper adjacent pixel, a down control signal (M_DN) for moving the image data to a lower adjacent pixel, a left control signal (M_LE) for moving the image data to a left adjacent pixel, and a right control signal (M_RI) for moving the image data to a right adjacent pixel. ### Claim 10 (depends on 9) The pixel of the display device according to claim 9, wherein the first path controller is configured to select: a connection path with a lower adjacent pixel for receiving data when the up control signal (M_UP) is received; a connection path with an upper adjacent pixel for receiving data when the down control signal (M_DN) is received; a connection path with a right adjacent pixel for receiving data when the left control signal (M_LE) is received; and a connection path with a left adjacent pixel for receiving data when the right control signal (M_RI) is received. ### Claim 11 (depends on 9) The pixel of the display device according to claim 9, wherein the second path controller is configured to select: a connection path with an upper adjacent pixel for shifting data when the up control signal (M_UP) is received; a connection path with a lower adjacent pixel for shifting data when the down control signal (M_DN) is received; a connection path with a left adjacent pixel for shifting data when the left control signal (M_LE) is received; and a connection path with a right adjacent pixel for shifting data when the right control signal (M_RI) is received. ### Claim 12 (depends on 7) The pixel of the display device according to claim 7, wherein the pixel-embedded memory comprises: a first dummy shift register configured to retrieve 1-bit data stored in the pixel-embedded memory of an adjacent pixel; n-bit shift registers configured to store n-bit image data; and a second dummy shift register configured to retrieve 1-bit data stored in the n-bit shift registers. ### Claim 13 (depends on 12) The pixel of the display device according to claim 12, wherein the first dummy shift register operates to retrieve 1-bit data from the pixel-embedded memory of the adjacent pixel at a first clock of the data movement time interval, the second dummy shift register operates to retrieve 1-bit data from the n-bit shift registers at a second clock of the data movement time interval, and each of the n-bit shift registers is configured to shift 1-bit data starting from a third clock of the data movement time interval. ### Claim 14 (depends on 12) The pixel of the display device according to claim 12, wherein the first dummy shift register and the second dummy shift register include a reset switch configured to reset the registers after the image data is moved. ### Claim 15 (depends on 1) The display device according to claim 1, wherein at least one of the plurality of pixels comprises: a plurality of output pins configured to output image data stored in the pixel-embedded memory to an adjacent pixel based on a control signal input from the controller during a data movement time interval; and a plurality of input pins configured to receive image data from an adjacent pixel. ### Claim 16 (depends on 15) The display device according to claim 15, wherein the plurality of output pins comprises: an up output pin (DO_U) configured to output image data to an upper adjacent pixel, a down output pin (DO_D) configured to output image data to a lower adjacent pixel, a left output pin (DO_L) configured to output image data to a left adjacent pixel, and a right output pin (DO_R) configured to output image data to a right adjacent pixel; and wherein the plurality of input pins comprises: a down input pin (DI_D) configured to receive image data from an upper adjacent pixel, an up input pin (DI_U) configured to receive image data from a lower adjacent pixel, a right input pin (DI_R) configured to receive image data from a left adjacent pixel, and a left input pin (DI_L) configured to receive image data from a right adjacent pixel. ### Claim 17 A display device comprising: a controller configured to control data writing, light-emitting element driving, and data movement; and a first pixel and a second pixel, wherein each of the first pixel and the second pixel includes a pixel-embedded memory configured to store image data represented by a multi-bit value, and wherein the pixel-embedded memory comprises: a first dummy shift register configured to retrieve 1-bit data stored in a pixel-embedded memory of an adjacent pixel; n-bit shift registers configured to store n-bit image data; and a second dummy shift register configured to retrieve 1-bit data stored in the n-bit shift registers during a data movement time interval. ### Claim 18 (depends on 17) The display device according to claim 17, wherein, when the first pixel and the second pixel are connected to a same column line, image data shift between left and right adjacent pixels is performed over n+1 line times. ### Claim 19 (depends on 18) The display device according to claim 18, wherein the first pixel is connected to a first column line, the second pixel is connected to a second column line, and when image data is shifted from the first pixel to the second pixel, the first pixel performs bit-wise shifting in the order of its first dummy shift register, second dummy shift register, and n-bit shift registers during a clock cycle of the first column line, and the second pixel performs bit-wise shifting in the order of its first dummy shift register, second dummy shift register, and n-bit shift registers during a clock cycle of the second line that is delayed by one line time relative to the clock cycle of the first column line.