DRAM Cache with Stacked, Heterogenous Tag and Data Dies
AssigneeRambus Inc.
InventorsTaeksang Song, Michael Raymond Miller, Steven C. Woo
Life of this patent
Estimating the term…
Abstract
A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit/miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit/miss determination for cache-line read/write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.
Claims21
1-22. (canceled)
A multi-die memory component comprising:
- a first dynamic random access memory (DRAM) die having a first plurality of mats, each mat of the first plurality of mats including a respective plurality of rows of DRAM cells and being characterized by a first minimum time interval between successive row activations;
- and
- a second DRAM die disposed in a stack with the first DRAM die and having a second plurality of mats, each mat of the second plurality of mats including a respective plurality of rows of DRAM cells and being characterized by a second minimum time interval between successive row activations, the second minimum time interval being not more than half the first minimum time interval.
A multi-die memory package comprising:
- a first dynamic random access memory (DRAM) die having a first memory core characterized by a first access latency;
- and
- a second DRAM die having a second memory core characterized by a second access latency, the second access latency being at least twice as long as the first access latency.
A stacked-die memory component comprising:
- a first dynamic random access memory (DRAM) die having a first memory core characterized by a first access latency;
- a plurality of additional DRAM dies having respective memory cores characterized by a second access latency at least twice as long as the first access latency;
- and
- conductors extending from the first DRAM die to each of the additional DRAM dies.
Dependencies are inferred from the claim text.