# US 2026/0099346 A1 · Speed enhancement system and method for computer mathmatics calculations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0099346 A1 - Document ID: US20260099346A1 - Status: Published application - Kind: A1 - Application number: 19/325,433 - Filed: 2025-09-10 - Published: 2026-04-09 - Earliest claimed: 2024-09-10 - Applicants: Hayan Software Accelerator LLC - Inventors: Nitin Vala - Web page: https://patentgrep.com/patent/US20260099346A1 ## CPC - G06F 9/45516: {Runtime code conversion or optimisation} - G06F 9/5016: {the resource being the memory} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5044: {considering hardware capabilities} - G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 9/522: {Barrier synchronisation} - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F 2209/5018: Thread allocation - G06F 2209/509: Offload - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present invention provides a method and system for constructing computer software to operate with a specific CPU chip architecture to improve the performance speed of the computer and software. By coding the software to operate with a specific CPU, the software can be caused to send the calculations through the CPU or GPU in a manner which results in a much faster result than would normally occur without the present system and method. The present system and method also better utilizes the full capacity of the CPU or GPU to make calculations, and increases the security of the computer for data transfers. ## Claims ### Claim 1 A software (100) for improving the speed of computations performed by a computer having a monitor, a keyboard, a pointer, hard memory, temporary memory, virtual memory, random access memory and at least one central processing unit (CPU) (15) comprising; the software (100) first analyzes the type of CPU (15), the software then determines a maximum random access memory (RAM) size, the software then determines the maximum number of memory channels and the maximum memory bandwidth provided by the hardware, next the software determines what the maximum CPU operating temperature is, the software determines whether there is a deep learning boost available on the CPU, how many cores there are in the CPU, if high priority cores are available, and what frequency the high priority cores are verses the number of low priority cores available in the CPU (15) and the availability of a CPU cache (19), wherein the software (100) analyzes the computer hardware components particularly with respect to the CPU (15) and modifies the software steps and sequences to improve the calculation speed of data passing through the computer system by modifying the calculation steps to conform to the computer hardware construction. ### Claim 2 (depends on 1) The software (100) for improving the speed of computer computations of claim 1 wherein after modifying the software (100) to better utilize the computer hardware, the software causes the data to be calculated to be decomposed into multiple kernels (20) to serve as a global synchronization point. ### Claim 3 (depends on 2) The software (100) for improving the speed of computer computations of claim 2 wherein recursive kernel invocation (22) can be utilized to process the data. ### Claim 4 (depends on 3) The software (100) for improving the speed of computer computations of claim 3 wherein a GFLOP(s) is/are utilized for compute-bound kernels (24) and a bandwidth is utilized for memory-bound kernels (26). ### Claim 5 (depends on 4) The software (100) for improving the speed of computer computations of claim 4 wherein the data is separated into thread blocks (14) for further processing. ### Claim 6 (depends on 5) The software (100) for improving the speed of computer computations of claim 5 wherein the software (100) includes an interleaved addressing (28) command wherein each thread block (14) loads one element from global memory (38) to shared memory (34) providing a reduction in shared memory, wherein the thread blocks are synced before the result is written to global memory (38). ### Claim 7 (depends on 5) The software (100) for improving the speed of computer computations of claim 5 wherein the software (100) further utilizes divergent branching (46) with the interleaved addressing, wherein the divergent branch is replaced in an inner loop with a strided index (50) and the non-divergent branch (52). ### Claim 8 (depends on 7) The software (100) for improving the speed of computer computations of claim 7 wherein the software (100) utilizes parallel reduction (10) with sequential addressing (54), wherein the sequential addressing (54) is accomplished by replacing the strided indexing (50) in the inner loop. ### Claim 9 (depends on 5) The software (100) for improving the speed of computer computations of claim 5 wherein the thread blocks (14) are loaded as two loads and a first add of the reduction reading from global memory (38) for writing to shared memory (34) to synchronize the thread blocks (14). ### Claim 10 (depends on 5) The software (100) for improving the speed of computer computations of claim 5 wherein the software (100) utilizes unrolling (82) when the thread (14) count is less than or equal to 32 threads. ### Claim 11 (depends on 10) The software (100) for improving the speed of computer computations of claim 10 wherein the number of iterations is known at compile time, allowing up to 512 threads (14) to be unrolled. ### Claim 12 (depends on 8) The software (100) for improving the speed of computer computations of claim 8 wherein the parallel reduction (10) is combined with sequential reduction to form algorithm cascading (92) wherein the data is combined and placed in shared memory (32). ### Claim 13 (depends on 1) The software (100) for improving the speed of computer computations of claim 1 wherein there is more than one central processing unit (15). ### Claim 14 (depends on 13) The software (100) for improving the speed of computer computations of claim 13 wherein the at least one central processing unit (15) includes at least one ultra path interconnect (UPI) for scaling multiprocessor systems with a shared address space. ### Claim 15 (depends on 14) The software (100) for improving the speed of computer computations of claim 14 wherein each processor includes at least three ultra path interconnects.