# US 2026/0099337 A1 · System Wakeup Method, Electronic Device, and Computer-Readable Storage Medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0099337 A1 - Document ID: US20260099337A1 - Status: Published application - Kind: A1 - Application number: 19/112,479 - Filed: 2023-12-01 - Published: 2026-04-09 - Earliest claimed: 2023-01-16 - Assignees: Honor Device Co., Ltd. - Applicants: Honor Device Co., Ltd. - Inventors: Jie Jin; Yanpei Liu; Jilin Liu; Yiang Xiong - Web page: https://patentgrep.com/patent/US20260099337A1 ## CPC - G06F 9/4418: {Suspend and resume; Hibernate and awake} - G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections - G06F 1/3215: Monitoring of peripheral devices - G06F 1/3237: by disabling clock generation or distribution - G06F 1/325: {Power saving in peripheral device} - G06F 13/4291: {using a clocked protocol} - H04W 52/0229: {where the received signal is a wanted signal} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) ## Abstract This application provides a system wakeup method, an electronic device, and a computer-readable storage medium. The method includes: monitoring a radio frequency front-end control bus in real time in a low power state; and sending a wakeup signal to a register status control module when a signal characteristic of a signal transmitted on the radio frequency front-end control bus meets a preset requirement, where the preset requirement is set based on a signal characteristic of an MIPI RFFE control instruction, and the wakeup signal is used to indicate the register status control module to output an enable signal, so that a system switches from the low power state to a working state or a standby state. When the signal characteristic transmitted on the radio frequency front-end control bus meets the preset requirement, it is determined that the electronic device is receiving the MIPI RFFE control instruction. Even when there is no clock source, the wakeup signal can be immediately sent to wake up the system, so that the system enters the working state or the standby state. This resolves a current problem that a part of the MIPI RFFE control instruction in a low power mode is lost or power consumption of the system is increased because the system is woken up in advance. ## Claims ### Claim 1 A system wakeup method, comprising: monitoring a radio frequency front-end (RFFE) control bus in real time in a low power state; and sending a wakeup signal to a register status control module when a signal characteristic of a signal transmitted on the RFFE control bus meets a preset requirement, wherein the preset requirement is set based on a signal characteristic of a mobile industry processor interface (MIPI) RFFE control instruction, and wherein the wakeup signal is configured to indicate to the register status control module to output an enable signal, so that a system switches from the low power state to a working state or to a standby state. ### Claim 2 (depends on 1) The method according to of claim 1, wherein the preset requirement is set in advance based on an instruction start flag of the MIPI RFFE control instruction. ### Claim 3 (depends on 2) The method of claim 2, wherein the RFFE control bus comprises a serial clock line and a serial data line, and wherein the signal characteristic of the signal transmitted on the RFFE control bus meets the preset requirement if no clock signal is received on the serial data line and a signal transmitted on the serial data line meets a characteristic of the instruction start flag. ### Claim 4 (depends on 1) The method of claim 1, wherein the register status control module is configured to modify, after receiving the wakeup signal, a status of an interrupt register, so that the interrupt register outputs the enable signal. ### Claim 5 (depends on 1) The method of claim 1, wherein after sending the wakeup signal to the register status control module, the enable signal is provided to a digital system clock phase locked loop module, so that the digital system clock phase locked loop module outputs a clock signal. ### Claim 6 (depends on 1) The method of claim 1, wherein after sending the wakeup signal to the register status control module, the enable signal is provided to a control module, so that the control module enters a configuration procedure of a gated clock control module, to enable clock gating. ### Claim 7 (depends on 1) The method of claim 1, wherein the wakeup signal is a control level. ### Claim 8 (depends on 7) The method of claim 7, wherein the control level is a high level or a low level. ### Claim at position 9 -11. (canceled) ### Claim 12 A terminal device, comprising: one or more processors; and one or more memories coupled to the one or more processors and configured to store instructions that, when executed by the one or more processors, cause the terminal device to be configured to: monitor a radio frequency front-end (RFFE) control bus in real time in a low power state; and send a wakeup signal to a register status control module when a signal characteristic of a signal transmitted on the RFFE control bus meets a preset requirement, wherein the preset requirement is set based on a signal characteristic of a mobile industry processor interface (MIPI) RFFE control instruction, and wherein the wakeup signal is configured to indicate to the register status control module to output an enable signal, so that a system switches from the low power state to a working state or to a standby state. ### Claim 13 (depends on 12) The terminal device of claim 12, wherein the preset requirement is set in advance based on an instruction start flag of the MIPI RFFE control instruction. ### Claim 14 (depends on 13) The terminal device of claim 13, wherein the RFFE control bus comprises a serial clock line and a serial data line, and wherein the signal characteristic of the signal transmitted on the RFFE control bus meets the preset requirement if no clock signal is received on the serial data line and a signal transmitted on the serial data line meets a characteristic of the instruction start flag. ### Claim 15 (depends on 12) The terminal device of claim 12, wherein the register status control module is configured to modify, after receiving the wakeup signal, a status of an interrupt register, so that the interrupt register outputs the enable signal. ### Claim 16 (depends on 12) The terminal device of claim 12, wherein after the wakeup signal is sent to the register status control module, the enable signal is provided to a digital system clock phase locked loop module, so that the digital system clock phase locked loop module outputs a clock signal. ### Claim 17 (depends on 12) The terminal device of claim 12, wherein after the wakeup signal is sent to the register status control module, the enable signal is provided to a control module, so that the control module enters a configuration procedure of a gated clock control module, to enable clock gating. ### Claim 18 (depends on 12) The terminal device of claim 12, wherein the wakeup signal is a control level. ### Claim 19 (depends on 18) The terminal device of claim 18, wherein the control level is a high level or a low level. ### Claim 20 A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors of a terminal device, cause the terminal device to be configured to: monitor a radio frequency front-end (RFFE) control bus in real time in a low power state; and send a wakeup signal to a register status control module when a signal characteristic of a signal transmitted on the RFFE control bus meets a preset requirement, wherein the preset requirement is set based on a signal characteristic of a mobile industry processor interface (MIPI) RFFE control instruction, and wherein the wakeup signal is configured to indicate to the register status control module to output an enable signal, so that a system switches from the low power state to a working state or to a standby state. ### Claim 21 (depends on 20) The non-transitory computer-readable storage medium of claim 20, wherein the preset requirement is set in advance based on an instruction start flag of the MIPI RFFE control instruction. ### Claim 22 (depends on 21) The non-transitory computer-readable storage medium of claim 21, wherein the RFFE control bus comprises a serial clock line and a serial data line, and wherein the signal characteristic of the signal transmitted on the RFFE control bus meets the preset requirement if no clock signal is received on the serial data line and a signal transmitted on the serial data line meets a characteristic of the instruction start flag. ### Claim 23 (depends on 20) The non-transitory computer-readable storage medium of claim 20, wherein the register status control module is configured to modify, after receiving the wakeup signal, a status of an interrupt register, so that the interrupt register outputs the enable signal.