# US 2026/0099331 A1 · Operand-less instruction set architecture-based processor and computer having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0099331 A1 - Document ID: US20260099331A1 - Status: Published application - Kind: A1 - Application number: 18/966,326 - Filed: 2024-12-03 - Published: 2026-04-09 - Earliest claimed: 2024-10-08 - Assignees: KoCOCOLINK INC. - Applicants: Cocolink Inc. - Inventors: Donghak LEE - Web page: https://patentgrep.com/patent/US20260099331A1 ## CPC - G06F 9/3802: {Instruction prefetching} - G06F 9/3001: {Arithmetic instructions} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/321: {Program or instruction counter, e.g. incrementing} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract It is disclosed that to an operand-less instruction set architecture-based processor and a computer having the operand-less instruction set architecture-based processor. An operand-less instruction set architecture-based processor includes an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit. ## Claims ### Claim 1 An operand-less instruction set architecture-based processor comprising: an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit. ### Claim 2 (depends on 1) The operand-less instruction set architecture-based processor of claim 1, wherein the instruction processing unit comprises: a program counter configured to store the memory address of the currently executing instruction, control the flow of the program, specify the address of the next instruction to execute, and increment the program counter value each time an instruction is executed to indicate the next instruction; an instruction loader configured to read instructions from external instruction memory; an instruction queue configured to store instructions loaded by the instruction loader, support continuous instruction processing, and provide quick access to instructions when needed; and an instruction processor configured to be respectively connected to the program counter, the instruction queue, and the functional processing unit. ### Claim 3 (depends on 2) The operand-less instruction set architecture-based processor of claim 2, wherein the program counter tracks the address of the next instruction by incrementing the counter based on the contents of the instruction queue. ### Claim 4 (depends on 2) The operand-less instruction set architecture-based processor of claim 2, wherein the instruction queue operates in units of bytes, and the instruction consists of 1 byte when there is no operand and 3 to 4 bytes when there is an operand to store the instruction. ### Claim 5 (depends on 2) The operand-less instruction set architecture-based processor of claim 2, wherein the instruction processor comprises: an instruction fetcher configured to read instructions from the instruction queue and provide them to the functional processing unit; an instruction disassembler configured to interpret instructions and convert them into executable form; and a function selector configured to activate function modules within the functional processing unit. ### Claim 6 (depends on 5) The operand-less instruction set architecture-based processor of claim 5, wherein the instruction disassembler processes instructions without an operand as a single byte and includes additional bytes in instructions with an operand to form a complete instruction. ### Claim 7 (depends on 1) The operand-less instruction set architecture-based processor of claim 1, wherein the functional processing unit comprises: a first functional processing module corresponding to an arithmetic logic unit (ALU) having an arithmetic function; and a second functional processing module corresponding to a control unit having a control function. ### Claim 8 (depends on 7) The operand-less instruction set architecture-based processor of claim 7, wherein the stacked register comprises: an ALU register accessed by the first functional processing module; and an FPU stack accessed by the stacker of the second functional processing module. ### Claim 9 (depends on 8) The operand-less instruction set architecture-based processor of claim 8, wherein the FPU stack comprises: a register stack accessed by a stacker; and an operation-only register operated by an ALU. ### Claim 10 (depends on 9) The operand-less instruction set architecture-based processor of claim 9, wherein the operation-only register comprises: a first direct access register that stores a first operand as input data; a second direct access register that stores a second operand as input data; and a result storage register that stores the result of an operation. ### Claim 11 (depends on 10) The operand-less instruction set architecture-based processor of claim 10, wherein the first direct access register is synchronized with, or identical to, the top of the register stack, and the second direct access register is synchronized with, or identical to, the next top of the register stack. ### Claim 12 (depends on 10) The operand-less instruction set architecture-based processor of claim 10, wherein the result storage register places the result value at the top of the register stack after the calculation operation is completed. ### Claim 13 An operand-less instruction set architecture-based computer comprising: an instruction memory configured to store the instructions of the program; a data memory configured to store data necessary for the execution of the program; and a processor configured to read the program instructions from the instruction memory and to receive and transmit data from the data memory, wherein the processor comprises: an instruction processing unit configured to process program instructions, but having no operand other than instructions for receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit. ### Claim 14 (depends on 13) The operand-less instruction set architecture-based computer of claim 13, wherein the instruction processing unit comprises: a program counter configured to store the memory address of the currently executing instruction, control the flow of the program, specify the address of the next instruction to execute, and increment the program counter value each time an instruction is executed to indicate the next instruction; an instruction loader configured to read instructions from external instruction memory; an instruction queue configured to store instructions loaded by the instruction loader, support continuous instruction processing, and provide quick access to instructions when needed; and an instruction processor configured to be respectively connected to the program counter, the instruction queue, and the functional processing unit. ### Claim 15 (depends on 14) The operand-less instruction set architecture-based computer of claim 14, wherein the program counter tracks the address of the next instruction by incrementing the counter based on the contents of the instruction queue. ### Claim 16 (depends on 14) The operand-less instruction set architecture-based computer of claim 14, wherein the instruction queue operates in units of bytes, and the instruction consists of 1 byte when there is no operand and 3 to 4 bytes when there is an operand to store the instruction. ### Claim 17 (depends on 14) The operand-less instruction set architecture-based computer of claim 14, wherein the instruction processor comprises: an instruction fetcher configured to read instructions from the instruction queue and provide them to the functional processing unit; an instruction disassembler configured to interpret instructions and convert them into executable form; and a function selector configured to activate function modules within the functional processing unit. ### Claim 18 (depends on 13) The operand-less instruction set architecture-based computer of claim 13, wherein the functional processing unit comprises: a first functional processing module corresponding to an arithmetic logic unit (ALU) having an arithmetic function; and a second functional processing module corresponding to a control unit having a control function. ### Claim 19 (depends on 18) The operand-less instruction set architecture-based computer of claim 18, wherein the stacked register comprises: an ALU register accessed by the first functional processing module; and an FPU stack accessed by the stacker of the second functional processing module. ### Claim 20 (depends on 19) The operand-less instruction set architecture-based computer of claim 19, wherein the FPU stack comprises: a register stack accessed by the stacker; and an operation-only register operated by the ALU.