Analog multiply-accumulate unit for multibit in-memory cell computing

A multibit in-memory compute circuit, comprising:

• a memory array comprising a plurality of bit cells to store a plurality of bits of a multibit value and output a plurality of digital signals corresponding to the plurality of bits;
• and
• a multibit multiplier circuit coupled to the memory array, the multibit multiplier circuit comprising at least a branch and a further branch;
• wherein:
• the branch includes:
• a capacitor,
• a switch controllable by a digital signal from a bit cell of the plurality of bit cells to electrically connect or disconnect an input analog signal to a side of the capacitor;
• and
• a further capacitor between a further side of the capacitor and the further branch;
• and
• the further branch includes:
• a yet further capacitor having a side coupled to the further capacitor and an output node of the multibit multiplier circuit;
• and
• a further switch controllable by a further digital signal from a further bit cell of the plurality of bit cells to electrically connect or disconnect the input analog signal to a further side of the yet further capacitor.

A multibit in-memory compute circuit, comprising:

• a memory array comprising a plurality of bit cells store a plurality of bits of a multibit value and output a plurality of digital signals corresponding to the plurality of bits;
• and
• a multibit multiplier circuit to receive the plurality of digital signals and an input analog signal;
• wherein:
• the multibit multiplier circuit comprises a plurality of capacitors, a plurality of further capacitors, a plurality of switches corresponding to the plurality of capacitors, and an output node;
• and
• the plurality of switches have a plurality of control terminals to receive the plurality of digital signals respectively to connect or disconnect the input analog signal to the plurality of capacitors respectively.

An in-memory multiply-and-accumulate circuit, comprising:

• a memory array to output a plurality of digital signals corresponding to a plurality of bits of a multibit weight of a neural network;
• a multibit multiplier circuit comprising a C2C ladder, wherein the plurality of digital signals selectively couple an input analog signal to a corresponding capacitor in the C2C ladder, and the C2C ladder outputs an output signal at an output node;
• a further memory array to output a plurality of further digital signals corresponding to a plurality of further bits of a further multibit weight;
• a further multibit multiplier circuit comprising a further C2C ladder, wherein the plurality of further digital signals selectively couple a further input analog signal to a corresponding capacitor in the C2C ladder, and the further C2C ladder outputs a further output signal at a further output node;
• and
• a summing node to connecting the output node and the further output node.