Multi-bit analog multiply-accumulate operations with memory crossbar arrays

A hardware processing apparatus, comprising

• a memory device having a crossbar array structure including K ×L cells interconnecting K rows and L columns, the cells including respective memory systems storing respective N-bit weights,
• K×L compute units) connected to respective ones of the memory systems of the K×L cells, wherein the compute units are configured as interleaved switched-capacitor analogue multipliers and adders;
• and
• an electronic circuit configured to synchronously apply input signals encoding respective M-bit input words to respective ones of the K rows, operate the compute units according to a 3-phase clocking scheme, and obtain multiply-accumulate results for each of the L columns, where K≥2, L≥2, N≥2, and M≥2, wherein the electronic circuit is further configured to
• set the clocking scheme to perform n×m partial multiplications, in an analogue domain, according to a bit partition decomposing each of the N-bit weights into n groups of bits and each of the M-bit input words into m groups of bits, wherein each of the n groups and the m groups includes at least one bit, but at least one of the n groups and/or the m groups includes at least two bits, whereby N+M>n+m≥3, so as to obtain n×m partial output signals, and
• obtain the multiply-accumulate results by summing the partial output signals obtained by the compute units for each of the L columns, converting the summed output signals into digital signals encoding partial values, shifting the partial values according to corresponding bit positions set in accordance with the bit partition, and adding the shifted values.

A computing system comprising:

• one or more hardware processing apparatuses;
• a memory unit;
• and
• a general-purpose processing unit connected to the memory unit to read data from, and write data to, the memory unit, wherein:
• each of the hardware processing apparatuses is configured to read data from, and write data to, the memory unit, and
• the general-purpose processing unit is configured to:
• map a given computing task to vectors and weights,
• instruct to store said weights as N-bit weights in cells of any of the hardware processing apparatuses, and
• instruct to apply input signals encoding vector components of such vectors as M-bit input words to rows of any of the hardware processing apparatuses, so as to perform such a computing task, in operation.