# US 2026/0096484 A1 · Semiconductor package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0096484 A1 - Document ID: US20260096484A1 - Status: Published application - Kind: A1 - Application number: 19/203,560 - Filed: 2025-05-09 - Published: 2026-04-02 - Earliest claimed: 2024-10-02 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Suk Won JANG; Jae Choon KIM - Web page: https://patentgrep.com/patent/US20260096484A1 ## CPC - H10W 90/00: Package configurations - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/40: characterised by their materials - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/74: {using temporarily an auxiliary support} - H10W 74/016: {using moulds} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package that includes a first redistribution structure; a logic die on the first redistribution structure; a plurality of conductive posts on the first redistribution structure, the plurality of conductive posts being laterally next to the logic die; a second redistribution structure on the logic die and the plurality of conductive posts; and a memory package on the second redistribution structure. The memory package includes a plurality of first bumps; a plurality of second bumps laterally next to the plurality of first bumps; an interposer on the plurality of first bumps, the interposer defining a through opening through the interposer; a heat dissipating structure on the plurality of second bumps, the heat dissipating structure being in the through opening; and a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure. ## Claims ### Claim 1 A semiconductor package comprising: a first redistribution structure; a logic die on the first redistribution structure; a plurality of conductive posts on the first redistribution structure, the plurality of conductive posts being laterally next to the logic die; a second redistribution structure on the logic die and the plurality of conductive posts; and a memory package on the second redistribution structure, wherein the memory package includes a plurality of first bumps, a plurality of second bumps laterally next to the plurality of first bumps, an interposer on the plurality of first bumps, the interposer defining a through opening through the interposer, a heat dissipating structure on the plurality of second bumps, the heat dissipating structure being in the through opening, and a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the plurality of second bumps are dummy bumps. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the plurality of second bumps are electrically disconnected from the second redistribution structure. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the plurality of second bumps are thermally connected to the heat dissipating structure and the second redistribution structure. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the heat dissipating structure includes: a main body; and an extension part extending from an external circumferential surface of the main body, the extension part being around the through opening and on an upper surface of the interposer. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the extension part laterally surrounds the through opening. ### Claim 7 (depends on 5) The semiconductor package of claim 5, wherein the memory package further includes an adhesive member between the interposer and the extension part. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the memory structure contacts the interposer. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the memory package further includes a plurality of third bumps between the memory structure and the interposer. ### Claim 10 A semiconductor package comprising: a first redistribution structure; a logic die on the first redistribution structure; a plurality of conductive posts on the first redistribution structure, the plurality of conductive posts being laterally next to the logic die; a second redistribution structure on the logic die and the plurality of conductive posts; and a memory package on the second redistribution structure, wherein the memory package includes a plurality of bumps, an interposer on the plurality of bumps, a heat dissipating structure on the interposer, and a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein a footprint of the heat dissipating structure overlaps a footprint of the logic die. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein the memory structure comprises a plurality of memory structures, and the heat dissipating structure is between the plurality of memory structures. ### Claim 13 (depends on 10) The semiconductor package of claim 10, wherein the memory structure includes a DRAM or a high bandwidth memory (HBM). ### Claim 14 A semiconductor package comprising: a front-side redistribution structure; a logic die on the front-side redistribution structure; conductive posts on the front-side redistribution structure, the conductive posts being laterally next to the logic die; a first molding material covering the logic die and the conductive posts on the front-side redistribution structure; a back-side redistribution structure on the conductive posts and the first molding material; a memory package on the back-side redistribution structure; and a second molding material covering the memory package on the back-side redistribution structure, wherein the memory package includes an interposer defining a through opening through the interposer, a plurality of first bumps between the back-side redistribution structure and the interposer, a heat dissipating structure in the through opening, a plurality of second bumps between the back-side redistribution structure and the heat dissipating structure, a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure, and a third molding material covering the memory structure on the interposer. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the memory package further includes a fourth molding material in the through opening, the fourth molding material being between the interposer and the heat dissipating structure, and between the third molding material and the heat dissipating structure. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein the third molding material includes a high dielectric constant molding material. ### Claim 17 (depends on 14) The semiconductor package of claim 14, wherein the back-side redistribution structure includes: a dielectric; a plurality of wire patterns in the dielectric; a plurality of dummy wire patterns in the dielectric; a plurality of bonding pads on the dielectric; and a plurality of dummy bonding pads on the dielectric, the plurality of dummy bonding pads being laterally next to the plurality of bonding pads. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the plurality of second bumps respectively contact corresponding dummy bonding pads among the plurality of dummy bonding pads. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the plurality of dummy wire patterns and the plurality of dummy bonding pads are thermally connected to the plurality of second bumps and the heat dissipating structure. ### Claim 20 (depends on 17) The semiconductor package of claim 17, wherein a footprint of the plurality of dummy wire patterns and the plurality of dummy bonding pads overlaps a footprint of the logic die.