# US 2026/0096239 A1 · Semiconductor devices and methods of formation

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- Number: US 2026/0096239 A1
- Document ID: US20260096239A1
- Status: Published application
- Kind: A1
- Application number: 18/903,220
- Filed: 2024-10-01
- Published: 2026-04-02
- Earliest claimed: 2024-10-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shen-Hui HONG; Ming-Tsong WANG; Jen-Cheng LIU
- Web page: https://patentgrep.com/patent/US20260096239A1

## CPC

- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10F 39/026: {Wafer-level processing}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A capacitor structure is included in an interconnect layer of a semiconductor die that is bonded to another semiconductor die in a vertical stack in a semiconductor die. To enable the vertical length of the capacitor structure to be increased, the top electrode layer of the capacitor structure is directly connected to a bonding structure of the semiconductor die as opposed to the top electrode layer of the capacitor structure being connected to the bonding structure through one or more intermediate conductive structures in the interconnect layer. This enables the capacitor structure to vertically extend through a greater quantity of layers of the interconnect layer, which increases the length of the top and bottom electrode layers of the capacitor structure, which increases the capacitance of the capacitor structure. The increased capacitance of the capacitor structure may enable increased performance for the semiconductor device to be achieved.

## Claims

### Claim 1

A semiconductor device, comprising:
a device layer;
one or more integrated circuit devices in the device layer;
an interconnect layer above the device layer;
one or more conductive structures in the interconnect layer;
one or more bonding structures above the interconnect layer; and
a trench capacitor structure directly coupled to a bonding structure of the one or more bonding structures.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the bonding structure comprises a bonding via;
wherein the one or more bonding structures comprises a bonding pad; and
wherein the bonding pad is coupled to the bonding via.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a top electrode layer of the trench capacitor structure is in contact with the bonding via; and
wherein a bottom electrode layer of the trench capacitor structure is in contact with a conductive structure of the one or more conductive structures.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a bottom surface of the bond via is recessed in the top electrode layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the bonding structure comprises a bonding pad.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a top electrode layer of the trench capacitor structure is in contact with the bonding pad; and
wherein a bottom electrode layer of the trench capacitor structure is in contact with a conductive structure of the one or more conductive structures.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a bottom surface of the bonding pad is recessed in the top electrode layer.

### Claim 8

A semiconductor package, comprising:
a first semiconductor die, comprising:
a first interconnect layer;
one or more first conductive structures in the first interconnect layer; and
a first plurality of bonding structures above the first interconnect layer; and
a trench capacitor structure directly coupled to a first bonding structure of the first plurality of bonding structures; and
a second semiconductor die bonded to the first semiconductor die at a bonding interface such that the first semiconductor die and the second semiconductor die are vertically arranged in the semiconductor package,
wherein the second semiconductor die comprises:
a second interconnect layer;
one or more second conductive structures in the second interconnect layer; and
a second plurality of bonding structures below the second interconnect layer,
wherein a second bonding structure of the second plurality of bonding structures is electrically coupled to the first bonding structure.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the first bonding structure comprises a first bonding pad; and
wherein the second bonding structure comprises a second bonding pad.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the first bonding pad is bonded to the second bonding pad; and
wherein the first bonding pad is laterally offset relative to the second bonding pad.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein the second semiconductor die further comprises:
a pixel sensor array that includes a plurality of pixel sensors,
wherein the trench capacitor structure is located under the pixel sensor array.

### Claim 12 (depends on 8)

The semiconductor package of claim 8, wherein the first bonding structure comprises a bonding via; and
wherein the second bonding structure comprises a bonding pad.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the bonding via is coupled to another bonding pad in the second semiconductor die; and
wherein the bonding pad in the second semiconductor die is bonded to the other bonding pad in the first semiconductor die.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the second semiconductor die further comprises:
a pixel sensor array that includes a plurality of pixel sensors,
wherein the trench capacitor structure is located under a periphery region that laterally surrounds the pixel sensor array.

### Claim 15 (depends on 8)

The semiconductor package of claim 8, wherein the second semiconductor die further comprises:
another trench capacitor structure directly coupled to a third bonding structure of the second plurality of bonding structures of the second semiconductor die,
wherein a fourth bonding structure of the first plurality of bonding structures of the first semiconductor die is electrically coupled to the third bonding structure of the second semiconductor die.

### Claim 16

A method, comprising:
forming one or more integrated circuit devices in a device layer of a semiconductor device;
forming an interconnect layer of the semiconductor device above the device layer;
forming a recess through a plurality of dielectric layers of the interconnect layer;
forming a trench capacitor structure of the semiconductor device in the recess; and
forming a bonding structure of the semiconductor device on the trench capacitor structure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
bonding the semiconductor device to another semiconductor device such that the bonding structure is directly bonded to another bonding structure of the other semiconductor device.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a bonding dielectric layer; and
forming the bonding structure through the bonding dielectric layer; and
bonding the semiconductor device to the other semiconductor device such that the bonding dielectric layer is directly bonded to another bonding dielectric layer around the other bonding structure of the other semiconductor device.

### Claim 19 (depends on 18)

The method of claim 18, wherein the bonding structure and the other bonding structure are misaligned such that a first portion of a bonding surface of the bonding structure is bonded to the other bonding structure, and such that a second portion of the bonding surface is in contact with the other bonding dielectric layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein forming the bonding structure comprises:
forming a bonding via on a top electrode layer of the trench capacitor structure,
wherein the method further comprises:
forming a bonding pad on the bonding via.