Semiconductor device with reverse current protection

A device, comprising:

• an n-type buried layer in a substrate;
• a first N-well region over the n-type buried layer;
• a p-type body region abutting the first N-well region;
• a first source/drain region in the first N-well region;
• a second source/drain region in the p-type body region;
• a gate structure extending across a boundary of the first N-well region and the p-type body region;
• a second N-well region over the n-type buried layer;
• a p-type region over the second N-well region;
• and
• a first silicide region interfacing the p-type region.

A method, comprising:

• forming a buried layer in a substrate, the buried layer being of a first conductivity type;
• forming an epitaxial layer over the buried layer;
• forming a first well region and a second well region in the epitaxial layer, the first and second well regions being of the first conductivity type;
• forming a body region over the buried layer, the body region forming a PN junction with the first well region;
• forming a first source/drain region in the first well region, and a second source/drain region in the body region;
• forming a gate structure laterally between the first source/drain region and the second source/drain region;
• and
• forming a first silicide region in contact with the second well region.