# US 2026/0096136 A1 · Method of forming high voltage transistor and structure resulting therefrom

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- Number: US 2026/0096136 A1
- Document ID: US20260096136A1
- Status: Published application
- Kind: A1
- Application number: 19/412,909
- Filed: 2025-12-09
- Published: 2026-04-02
- Earliest claimed: 2023-01-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: LING MEI LIN; YU-CHANG JONG; CHIH-HSIUNG HUANG; YU-HSIEN CHU; WEN-CHIH CHIANG; CHIH-MING LEE; CHENG-MING WU; PEI-LUN WANG
- Web page: https://patentgrep.com/patent/US20260096136A1

## CPC

- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/028: {of double-diffused metal oxide semiconductor [DMOS] FETs}
- H10D 62/103: {for increasing or controlling the breakdown voltage of reverse-biased devices}
- H10D 62/152: {Source regions of DMOS transistors}
- H10D 62/156: {Drain regions of DMOS transistors}
- H10D 64/01: Manufacture or treatment
- H10D 64/514: {characterised by the insulating layers}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6328: {Deposition from the gas or vapour phase}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/282: {of inorganic materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 70/23: {during, before or after processing of insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor substrate;
a gate dielectric layer over the semiconductor substrate; and
a gate electrode over the gate dielectric layer,
wherein the gate dielectric layer comprises a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion comprises a third portion comprising nitrogen and enclosed by the first portion.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, further comprising forming a gate spacer laterally surrounding the gate electrode.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein the third portion is higher than the second portion.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein a lateral side of the first portion is exposed through the gate electrode.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, wherein the first portion has a first thickness, the second portion has a second thickness, and a thickness ratio between the first thickness and the second thickness is between about 1.5 and about 3.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein the first portion and the second portion are formed of a same material.

### Claim 7 (depends on 6)

The semiconductor structure according to claim 6, wherein the same material is silicon oxide.

### Claim 8 (depends on 1)

The semiconductor structure according to claim 1, wherein the first portion covers and laterally surrounds the third portion in a conformal manner.

### Claim 9 (depends on 1)

The semiconductor structure according to claim 1, wherein the third portion has a gradient concentration of nitrogen in a vertical direction.

### Claim 10 (depends on 1)

The semiconductor structure according to claim 1, wherein the first portion comprises a first bottom surface, and the second portion comprises a second bottom surface lower than the first bottom surface.

### Claim 11

A semiconductor structure, comprising:
a substrate;
a first dielectric layer over the substrate;
a second dielectric layer over the first dielectric layer;
a third dielectric layer within the second dielectric layer, wherein the second dielectric layer comprises an element with a first concentration in the third dielectric layer greater than a second concentration of the element in other portions of the second dielectric layer; and
a first gate electrode over the first dielectric layer and the second dielectric layer.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, wherein the element is nitrogen.

### Claim 13 (depends on 11)

The semiconductor structure according to claim 11, wherein the second dielectric layer comprises an oxygen concentration in the third dielectric layer lower than that in the other portions of the second dielectric layer.

### Claim 14 (depends on 11)

The semiconductor structure according to claim 11, wherein, the second dielectric layer covers an entirety of a lateral side and an upper surface of the third dielectric layer.

### Claim 15 (depends on 11)

The semiconductor structure according to claim 11, further comprising a first source/drain region and a second source/drain region in the substrate on two sides of the first gate electrode, wherein the second dielectric layer is higher than the third dielectric layer and is closer to the first source/drain region than to the second source/drain region.

### Claim 16 (depends on 11)

The semiconductor structure according to claim 11, further comprising a barrier layer and a doped region in the substrate, wherein the barrier layer and the doped region are connected to form a guard ring of the semiconductor structure.

### Claim 17 (depends on 11)

The semiconductor structure according to claim 11, further comprising:
a fourth dielectric layer over the substrate adjacent to the first dielectric layer;
a fifth dielectric layer over the fourth dielectric layer;
a sixth dielectric layer within the fifth dielectric layer, wherein the fifth dielectric layer comprises a nitrogen concentration in the sixth dielectric layer greater than that in other portions of the fifth dielectric layer; and
a second gate electrode over the fourth dielectric layer and the fifth dielectric layer.

### Claim 18

A semiconductor structure, comprising:
a barrier layer in a substrate;
a gate dielectric layer over the substrate, the gate dielectric layer comprising a first portion and a second portion, wherein the first portion is thicker than the second portion, wherein the first portion comprises a first material and a second material different from the first material and wrapped around by the first material;
a gate electrode over the gate dielectric layer; and
a gate spacer on two sides of the gate electrode.

### Claim 19 (depends on 18)

The semiconductor structure according to claim 18, wherein the first portion has a first depth extending into the substrate, and the second portion has a second depth, greater than the first depth, extending into the substrate.

### Claim 20 (depends on 18)

The semiconductor structure according to claim 18, wherein the gate electrode has a first region directly over the first portion and a second region directly over the second portion, wherein the first region has an upper surface higher than an upper surface of the second region.