Three-dimensional memory devices

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a peripheral circuit and a first bonding layer over the peripheral circuit;
• a second semiconductor structure comprising:
• a memory stack comprising interleaved conductive layers and dielectric layers;
• an N-type doped semiconductor layer above the memory stack;
• channel structures each extending vertically through the memory stack, each of the channel structures comprising a semiconductor channel extending into the N-type doped semiconductor layer and being in contact with the N-type doped semiconductor layer;
• a source contact in contact with the N-type doped semiconductor layer, the source contact and the memory stack being arranged at opposite sides of the N-type doped semiconductor layer;
• and
• a second bonding layer disposed over a side of the memory stack away from the N-type doped semiconductor layer, the second bonding layer being bonded with the first bonding layer,
• wherein:
• the memory stack comprises staircase structures each comprising a pair of a conductive layer and a dielectric layer, the conductive layer and the dielectric layer of the pair of the conductive layer and the dielectric layer extending laterally perpendicular to the channel structures and ending at a staircase structure;
• and
• a first extending length of a first staircase structure is larger than a second extending length of a second staircase structure, the second staircase structure being closer to the N-type doped semiconductor layer than the first staircase structure.