US 2026/0095205 A1Published application

Single wire serial interface and protocol for intra-chip communications

AssigneeSTMicroelectronics International N.V.

InventorsAnkur BAL, Rupesh SINGH, Parisha ARORA

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Abstract

Pulses having a first width and a second width greater than the first width are generated from a clock signal. An encoded data stream transmitted over a single communications wire is generated by: selecting the pulse having the first width for each bit of the transmit serial data stream having a first logic state; and selecting the pulse having the second width for each bit of the transmit serial data stream having a second logic state. Pulses of the received encoded data stream having the second width are then detected. A first flip-flop logic state is toggled in response to each detected pulse having the second width. A second flip-flop latches the first flip-flop logic state in response to each pulse of the encoded data stream. Outputs of the first and second flip-flops are logically combined to generate a receive serial data stream corresponding to the transmit serial data stream.

Claims16

Dependent claims

A communications system, comprising:

a transmitter circuit having an output;
a receive circuit having an input;
and
a single communications wire connecting the transmitter circuit output and the receiver circuit input;
wherein the transmitter circuit comprises:
a first delay line having an input configured to receive a first clock signal;
a second delay line having an input configured to receive a first delayed first clock signal output from the first delay line;
a first logic gate configured to logically combine the first clock signal and the first delayed first clock signal;
a second logic gate configured to logically combine the first clock signal and a second delayed first clock signal output from the second delay line;
and
a first multiplexer having a first input coupled to receive an output of the first logic gate and a second input coupled to receive an output of the second logic gate, wherein a selection control input of the first multiplexer receives a transmit serial data stream, and wherein an output of the first multiplexer generates an encoded data stream applied at the output of the transmitter circuit to the single communications wire;
and
wherein the receiver circuit comprises:
a third delay line having an input configured to receive the encoded data stream;
a third logic gate configured to logically combine the encoded data stream with a delayed encoded data stream output from the third delay line;
a first flip-flop configured as a toggle and having a clock input coupled to receive an output of the third logic gate;
a second flip-flip having an input coupled to an output of the first flip-flop and having a clock input coupled to receive the encoded data stream;
and
a fourth logic gate configured to logically combine the output of the first flip-flop and an output of the second flip-flop to generate a receive serial data stream corresponding to the transmit serial data stream.

16 more elements

Dependencies are inferred from the claim text.