Sar pipeline analog-to-digital converter (adc) with foreground self-calibration
AssigneeNXP USA, Inc.
InventorMichael Todd Berens
Life of this patent
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Abstract
A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.
Claims20
A pipelined successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
- a front-end ADC stage comprising a front-end digital-to-analog converter (DAC) connected to receive an analog input voltage and configured to output a residue voltage signal and to generate a first ADC conversion result by sampling and converting the analog input voltage with a front-end SAR circuit block;
- a residue amplifier connected to receive the residue voltage signal and to generate an amplified residue voltage signal;
- a back-end ADC stage comprising a back-end DAC connected to receive the amplified residue voltage signal and configured to generate a second ADC conversion result by sampling and converting the amplified residue voltage signal with a back-end SAR circuit block;
- and
- calibration circuitry coupled and configured to add the first and second ADC conversion results to form an uncalibrated digital value, and to apply a plurality of calibration values to digitally adjust the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage,
- where the plurality of calibration values comprises:
- a DAC element mismatch calibration value corresponding to the first ADC conversion result,
- an offset calibration value comprising a residue amplifier offset value and a back-end ADC stage offset value, and
- a gain adjustment factor.
A foreground self-calibration method for calibrating a pipelined successive approximation analog-to-digital converter (SAR ADC) comprising a front-end ADC stage connected over a residue amplifier to a back-end ADC stage, the foreground self-calibration method comprising:
- computing an offset calibration value for the residue amplifier and back-end ADC stage by using the back-end ADC stage to provide a digital measure of the offset voltage of the residue amplifier and back-end ADC stage;
- computing an element mismatch calibration value for each digital-to-analog converter (DAC) element in a front-end DAC of the front-end ADC stage by switching a plurality of DAC elements in the front-end DAC to generate a residue voltage input to the residue amplifier that is roughly in the range of −1 to +1 least significant bit (LSB) of the front-end ADC stage and using the back-end ADC stage to measure an amplified residue voltage generated by the residue amplifier after for each selected DAC element being calibrated;
- computing one or more summed calibration values for one or more first ADC conversion results based on one or more of the computed element mismatch calibration values;
- and
- computing a gain adjustment value based on a total sum of all DAC elements in the front-end ADC stage that are used to sample an analog input voltage.
A pipelined successive approximation register analog-to-digital converter (SAR ADC) comprising a front-end ADC connected over a residue amplifier to a back-end ADC:
- wherein the front-end ADC comprises:
- a first digital-to-analog converter (DAC) configured to receive a first input voltage signal, a high voltage reference, and a low voltage reference, and to generate therefrom a first DAC output, wherein the first DAC comprises a plurality of bits encoded with one or more first DAC capacitors,
- a first comparator having a first input coupled to receive the first DAC output, a second input, and a first comparator output, the first comparator configured to generate a differential comparison of the first and second inputs at the first comparator output, and
- a successive-approximation-register (SAR) logic and calibration control block having an input coupled to receive the first comparator output, wherein the SAR logic and calibration control block is configured to provide a first ADC conversion result representation of the analog input voltage and to generate feedback control signals to the first DAC;
- and
- wherein the back-end ADC comprises:
- a second DAC configured to receive an amplified residue voltage from the residue amplifier, a high voltage reference, and a low voltage reference, and to generate therefrom a second DAC output, wherein the second DAC comprises a plurality of bits encoded with one or more second DAC capacitors, and
- a second comparator having a first input coupled to receive the first DAC output, a second input, and a second comparator output, the second comparator configured to generate a differential comparison of the first and second inputs at the second comparator output;
- wherein the SAR logic and calibration control block is configured to provide control signals to the front-end ADC and back-end ADC to measure an offset calibration value for the residue amplifier and back-end ADC by tri-stating input terminals into the residue amplifier to create a residue voltage that the residue amplifier amplifies for sampling and conversion by the back-end ADC.
Dependencies are inferred from the claim text.