# US 2026/0095166 A1 · Consistency checking circuit for components with internal clocking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0095166 A1 - Document ID: US20260095166A1 - Status: Published application - Kind: A1 - Application number: 18/904,594 - Filed: 2024-10-02 - Published: 2026-04-02 - Earliest claimed: 2024-10-02 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Nicolaas Klarinus Johannes van Winkelhoff; Nicolas Patrick Alain Garnier - Web page: https://patentgrep.com/patent/US20260095166A1 ## CPC - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03K 5/1534: Transition or edge detectors - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A consistency checking circuit can include a dynamic input comparator structured to compare dynamic signals received at a first input and a second input to detect an inconsistency on an internal clock line of a component with respect to a signal from an external clock line, wherein the dynamic input comparator is coupled at the first input to the internal clock line and coupled at the second input to an external clock line of the component. The detected inconsistency can be a glitch on the internal clock line, a slew, or an inconsistent sequence of transitions. ## Claims ### Claim 1 An apparatus comprising: a dynamic input comparator structured to compare dynamic signals received at a first input and a second input to detect an inconsistency on an internal clock line of a component with respect to a signal from an external clock line, wherein the dynamic input comparator is coupled at the first input to the internal clock line and coupled at the second input to an external clock line of the component. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the internal clock line is coupled to clock circuitry that generates an internal clock signal on the internal clock line based on a signal from the external clock line. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the inconsistency on the internal clock line of the component with respect to the signal from the external clock line is a glitch on the internal clock line, a slew, or an inconsistent sequence of transitions. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising: logic circuitry structured to combine an external clock signal with a component enable signal and output the signal from the external clock line, wherein the second input of the dynamic input comparator is coupled to the external clock line through the logic circuitry. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the dynamic input comparator comprises: an edge detector circuit structured to receive an internal clock signal from the first input; a first AND gate having an inverted input and a regular input; and a second AND gate, wherein an output of the edge detector circuit is coupled to the regular input of the first AND gate and one input of the second AND gate, wherein the inverted input of the first AND gate and one other input of the second AND gate are coupled to the external clock line from the second input, wherein a first output of the first AND gate indicates detection of an inconsistency on the internal clock line. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the edge detector circuit is a rising edge detector. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the edge detector circuit is a falling edge detector. ### Claim 8 (depends on 5) The apparatus of claim 5, wherein the edge detector circuit comprises a trim input including a LC filter, Schmitt trigger, or configurable delay chain. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the dynamic input comparator comprises: a digital comparator; a first storage unit coupled to the internal clock line from the first input to capture a value indicating a received pulse; and a second storage unit coupled to the external clock line from the second input to capture a corresponding value indicating a received clock, wherein the digital comparator compares the value stored in the first storage unit with the corresponding value from the second storage unit and outputs a non-matching signal when the value and the corresponding value do not match, wherein the non-matching signal indicates the inconsistency on the internal clock line. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first storage unit and the second storage unit comprise latches. ### Claim 11 (depends on 1) The apparatus of claim 1, further comprising the component. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the component comprises memory circuitry. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the component comprises analog circuitry. ### Claim 14 (depends on 1) The apparatus of claim 1, further comprising: control logic coupled to the dynamic input comparator to receive an output of the dynamic input comparator, the output of the dynamic input comparator indicating whether the inconsistency is detected on the internal clock line. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the control logic triggers a restart function of the component in response to the output of the dynamic input comparator indicating the inconsistency is detected on the internal clock line. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the control logic triggers a shutdown of at least the component in response to the output of the dynamic input comparator indicating the inconsistency is detected on the internal clock line. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein the control logic triggers a change to a state of the component in response to the output of the dynamic input comparator indicating the inconsistency is detected on the internal clock line. ### Claim 18 (depends on 14) The apparatus of claim 14, wherein the control logic triggers a change to stored data of the component in response to the output of the dynamic input comparator indicating the inconsistency is detected on the internal clock line. ### Claim 19 (depends on 1) The apparatus of claim 1, wherein the component has inputs for a plurality of external clock lines including the external clock line, the apparatus further comprising: at least one additional dynamic input comparator, each additional dynamic input comparator of the at least one additional dynamic input comparator coupled to the internal clock line and a corresponding additional external clock line of the plurality of external clock lines; and a logic gate coupled to the dynamic input comparator and the at least one additional dynamic input comparator to combine outputs of the dynamic input comparator and the at least one additional dynamic input comparator. ### Claim 20 (depends on 1) The apparatus of claim 1, wherein the component has inputs for a plurality of external clock lines including the external clock line, the apparatus further comprising: a logic gate coupled to the plurality of external clock lines to combine signals from the plurality of external clock lines, wherein the dynamic input comparator is coupled at the second input to the external clock line of the component and to other external clock lines of the plurality of external clock lines via an output of the logic gate, whereby the dynamic input comparator detects the inconsistency on the internal clock line of the component with respect to the signal from the external clock line and any other signal from the other external clock lines of the plurality of external clock lines.