# US 2026/0094635 A1 · Memory using ferroelectric or antiferroelectric capacitors and diodes in stacked configurations

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- Number: US 2026/0094635 A1
- Document ID: US20260094635A1
- Status: Published application
- Kind: A1
- Application number: 18/900,295
- Filed: 2024-09-27
- Published: 2026-04-02
- Earliest claimed: 2024-09-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Sou-Chi Chang; Uygar Avci; Yu-Ching Liao; Ilya Karpov; Chia-Ching Lin; Gihun Choe
- Web page: https://patentgrep.com/patent/US20260094635A1

## CPC

- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2259: {Cell access}
- H10B 51/30: characterised by the memory core region
- H10B 51/40: characterised by the peripheral circuit region
- H10B 53/30: characterised by the memory core region
- H10B 53/40: characterised by the peripheral circuit region
- H10B 63/22: {of the metal-insulator-metal type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An integrated circuit die includes a first surface having conductive features and a second surface opposite the first surface. A device layer is proximate the first surface and includes a plurality of transistors. The device layer is between a memory layer and the first surface. The memory layer includes memory circuitry having a plurality of memory cells memory cells arranged in a cross-bar array. Each memory cell comprises first and second diodes, and a capacitor. Each diode includes an insulator material between electrodes. In some embodiments, the first and second diodes share an electrode. The capacitor includes a ferroelectric or an antiferroelectric material between electrodes.

## Claims

### Claim 1

An integrated circuit (IC) die, comprising:
a first surface comprising conductive features and a second surface opposite the first surface;
memory circuitry comprising a plurality of memory cells, each memory cell comprising first and second diodes, and a capacitor, the capacitor comprising a ferroelectric (FE) or an antiferroelectric (AFE) material;
a device layer proximate the first surface, the device layer comprising a plurality of transistors; and
a memory layer over the device layer, the memory layer comprising the memory circuitry.

### Claim 2 (depends on 1)

The IC die of claim 1, wherein the memory layer comprises a first layer and a second layer, the first and second diodes are in the first layer, the capacitor is in the second layer; and
the first layer is over the second layer, or the second layer is over the first layer.

### Claim 3 (depends on 2)

The IC die of claim 2, further comprising first and second word lines proximate the first layer and a bit line proximate the second layer.

### Claim 4 (depends on 1)

The IC die of claim 1, wherein:
the first diode comprises a first insulator material between a first electrode and a shared electrode;
the second diode comprises a second insulator material between a second electrode and the shared electrode; and
the capacitor comprises the FE or AFE material between third and fourth electrodes.

### Claim 5 (depends on 4)

The IC die of claim 4, further comprising a metal feature directly contacting the shared electrode and third electrode.

### Claim 6 (depends on 4)

The IC die of claim 4, wherein the shared electrode is directly on the third electrode.

### Claim 7 (depends on 4)

The IC die of claim 4, wherein a portion of the first electrode, a portion of the second electrode, and a portion of the shared electrode are all in a same layer.

### Claim 8 (depends on 4)

The IC die of claim 4, wherein the first electrode and the second electrode are in a same layer over the shared electrode.

### Claim 9 (depends on 1)

The IC die of claim 1, wherein:
the first diode comprises a first insulator material between first and second electrodes;
the second diode comprises a second insulator material between third and fourth electrodes; and
the capacitor comprises the FE or AFE material between fifth and sixth electrodes.

### Claim 10 (depends on 9)

The IC die of claim 9, wherein a portion of the first electrode and a portion of the second electrode are laterally adjacent to one another.

### Claim 11 (depends on 9)

The IC die of claim 9, wherein:
the first and second electrodes are in distinct layers and the second electrode is over the first electrode; and
the third and fourth electrodes are in distinct layers and the fourth electrode is over the third electrode.

### Claim 12 (depends on 9)

The IC die of claim 9, wherein the first diode is over the second diode.

### Claim 13 (depends on 1)

The IC die of claim 1, wherein:
the first diode comprises a first insulator material between first and second electrodes;
the second diode comprises a second insulator material between third and fourth electrodes;
the first electrode comprises a first interfacial layer contacting the first insulator material;
the third electrode comprises a second interfacial layer contacting the second insulator material; and
the first and second interfacial layers comprise a metal oxide.

### Claim 14 (depends on 1)

The IC die of claim 1, wherein the FE material and the AFE comprise hafnium, zirconium, or lanthanum.

### Claim 15 (depends on 1)

The IC die of claim 1, wherein:
the first diode comprises first material layers between first and second electrodes, the first material layers comprising:
a p-type polycrystalline semiconductor material layer, and
an n-type polycrystalline semiconductor material layer; and
the second diode comprises second material layers between third and fourth electrodes, the second material layers comprising:
a p-type polycrystalline semiconductor material layer, and
an n-type polycrystalline semiconductor material layer.

### Claim 16

An integrated circuit (IC) die, comprising:
a device layer comprising a plurality of transistors;
a memory array comprising a plurality of memory cells, each memory cell comprising:
a first diode in a first layer comprising a first insulator material between a first electrode and a shared electrode, the first diode further comprising a first interfacial layer contacting the shared electrode;
a second diode in the first layer comprising a second insulator material between a second electrode and the shared electrode, the second diode further comprising a second interfacial layer contacting the second electrode; and
a capacitor comprising a ferroelectric or an antiferroelectric material in a second layer; and
wherein the device layer is between the first layer and the second layer and a surface of the IC die.

### Claim 17 (depends on 16)

The IC die of claim 16, wherein a portion of the first electrode and a portion of the second electrode are laterally adjacent to one another.

### Claim 18

A system comprising:
an integrated circuit (IC) die, comprising:
memory circuitry comprising a plurality of memory cells, each memory cell comprising first and second diodes, and a capacitor, the capacitor comprising a ferroelectric (FE) or an antiferroelectric (AFE) material;
a device layer comprising a plurality of transistors;
a memory layer comprising the memory circuitry, wherein the device layer is between the memory layer and a surface of the IC die; and
a power supply coupled to the IC die to power the IC die.

### Claim 19 (depends on 18)

The system of claim 18, wherein:
the first diode comprises first electrode and a shared electrode;
the second diode comprises a second electrode and the shared electrode, wherein the shared electrode comprises a surface comprising a first portion adjacent to the first electrode and a second portion adjacent to the second electrode.

### Claim 20 (depends on 18)

The system of claim 18, wherein:
the first diode comprises first and second electrodes;
the second diode comprises a third electrode and a fourth electrode, wherein the first electrode comprises a first surface horizontally adjacent to the second electrode, and
the third electrode comprises a second surface horizontally adjacent to the fourth electrode.