Clock stabilization circuit, system, and operating method of system
AssigneeSK hynix Inc.
InventorJae Hoon JUNG
Life of this patent
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Abstract
A clock stabilization circuit includes a shift register configured to output one or more shifting signals by shifting data and an inversion flag based on a clock signal, a comparison circuit configured to output one or more comparison signals by comparing the one or more shifting signals with one or more keys, respectively, a stable flag register configured to enable a stable flag based on a first-delayed clock signal and the one or more comparison signals, the first-delayed clock signal generated by delaying the clock signal, and a mask circuit configured to output an internal clock signal by masking a second-delayed clock signal based on the stable flag, the second-delayed clock signal generated by delaying the first-delayed clock signal.
Claims19
A clock stabilization circuit comprising:
- a shift register configured to output one or more shifting signals by shifting data and an inversion flag based on a clock signal;
- a comparison circuit configured to output one or more comparison signals by comparing the one or more shifting signals with one or more keys, respectively;
- a stable flag register configured to enable a stable flag based on a first-delayed clock signal and the one or more comparison signals, the first-delayed clock signal generated by delaying the clock signal;
- and
- a mask circuit configured to output an internal clock signal by masking a second-delayed clock signal based on the stable flag, the second-delayed clock signal generated by delaying the first-delayed clock signal.
A system comprising:
- a first device configured to output data and an inversion flag, which are synchronized with a clock signal;
- and
- a second device configured to identify one or more initial patterns in a combination of the data and the inversion flag and generate an internal clock signal based on second clock cycles after first clock cycles synchronized with the one or more initial patterns in the clock signal.
An operating method of a system, the operating method comprising:
- outputting, by a first device, data and an inversion flag, which are synchronized with a clock signal;
- identifying, by a second device, one or more initial patterns in a combination of the data and the inversion flag;
- and
- generating, by the second device, an internal clock signal based on second clock cycles after first clock cycles synchronized with the one or more initial patterns in the clock signal.
Dependencies are inferred from the claim text.