Skew balancing among circuit signal pathways
AssigneeTexas Instruments Incorporated
InventorsTejas Salunkhe, Subhadeep Aich, Abhranil Bose
Life of this patent
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Abstract
Provided herein are various enhancements for skew balancing in semiconductor circuits, such as during the synthesis, timing, routing, and phases of circuit design. In one example implementation, a method includes simulating a circuit to determine initial path delay values for a set of paths in the circuit, and determining a reference value for the set of paths based on the initial path delay values. The method also includes generating constraints using the reference value and a skew target for the set of paths, and performing a timing analysis to redesign the circuit using the constraints.
Claims20
A method comprising:
- simulating a circuit to determine initial path delay values for a set of paths in the circuit;
- determining a reference value for the set of paths based on the initial path delay values;
- generating constraints using the reference value and a skew target for the set of paths;
- and
- performing a timing analysis to redesign the circuit using the constraints.
An apparatus, comprising:
- one or more non-transitory computer readable storage media;
- program instructions stored on the one or more non-transitory computer readable storage media, the program instructions executable by a processing system to direct the processing system to at least:
- simulate a circuit to determine initial path delay values for a set of paths in the circuit;
- determine a reference value for the set of paths based on the initial path delay values;
- generate constraints using the reference value and a skew target for the set of paths;
- and
- perform a timing analysis to redesign the circuit using the constraints.
A method, comprising:
- obtaining initial path delay values with path identifiers for a set of paths in a circuit;
- determining a reference value for the set of paths based on the initial path delay values;
- selecting a mean path delay mode, a minimum path delay mode, or a maximum path delay mode;
- generating constraints for the selected mode using the reference value and a skew target for the set of paths, wherein the constraints include a minimum path delay constraint or a maximum path delay constraint;
- and
- providing indications of the constraints for the path identifiers.
Dependencies are inferred from the claim text.