# US 2026/0093771 A1 · Efficient one-dimensional (1d) convolution support on two-dimensional (2d) convolution engines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093771 A1 - Document ID: US20260093771A1 - Status: Published application - Kind: A1 - Application number: 18/905,058 - Filed: 2024-10-02 - Published: 2026-04-02 - Earliest claimed: 2024-10-02 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Haoping XU - Web page: https://patentgrep.com/patent/US20260093771A1 ## CPC - G06F 17/15: Correlation function computation {including computation of convolution operations (arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00)} - G06N 3/063: using electronic means - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A processor-implemented method for efficient convolution operations includes receiving, by an artificial neural network, an input. The input is mapped to a multiple row input based on a processing capacity of a compute device. The compute device performs concurrent convolution operations according to the multiple row input. An output is generated based on the concurrent convolution operations. ## Claims ### Claim 1 An apparatus, comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor configured to: receive, by an artificial neural network, an input; map the input to a multiple row input based at least in part on a processing capacity of a compute device; perform, by the compute device, concurrent convolution operations according to the multiple row input; and generate an output based on the concurrent convolution operations. ### Claim 2 (depends on 1) The apparatus of claim 1, in which the input comprises a one-dimensional tensor. ### Claim 3 (depends on 1) The apparatus of claim 1, in which the at least one processor is further configured to compute, by a multiply-accumulate (MAC) unit of a neural processing unit, the concurrent convolution operations according to the multiple row input. ### Claim 4 (depends on 1) The apparatus of claim 1, in which the at least one processor is further configured to map the input into the multiple row input by adapting fetching of the input from memory. ### Claim 5 (depends on 1) The apparatus of claim 1, in which the input includes hardware padding before a first element of the input or after a last element of the input. ### Claim 6 (depends on 5) The apparatus of claim 5, in which the at least one processor is further configured to: split the input into multiple portions; remap a first portion of the input without the hardware padding into the multiple row input; and process a second portion of the input, the second portion including the hardware padding, without mapping the second portion to the multiple row input. ### Claim 7 (depends on 1) The apparatus of claim 1, in which the input comprises a multi-dimensional input. ### Claim 8 A processor-implemented method performed by one or more processors, the processor-implemented method comprising: receiving, by an artificial neural network, an input; mapping the input to a multiple row input based at least in part on a processing capacity of a compute device; performing, by the compute device, concurrent convolution operations according to the multiple row input; and generating an output based on the concurrent convolution operations. ### Claim 9 (depends on 8) The processor implemented method of claim 8, in which the input comprises a one-dimensional tensor. ### Claim 10 (depends on 8) The processor-implemented method of claim 8, in which the compute device comprises a multiply-accumulate (MAC) unit of a neural processing unit. ### Claim 11 (depends on 8) The processor-implemented method of claim 8, in which the input is mapped into multiple rows by adapting fetching of the input from memory. ### Claim 12 (depends on 8) The processor-implemented method of claim 8, in which the input includes hardware padding before a first element of the input or after a last element of the input. ### Claim 13 (depends on 12) The processor-implemented method of claim 12, further comprising: splitting the input into multiple portions; remapping a first portion of the input without the hardware padding into the multiple row input; and processing a second portion of the input, the second portion including the hardware padding, without mapping the second portion to the multiple row input. ### Claim 14 (depends on 8) The processor-implemented method of claim 8, in which the input comprises a multi-dimensional input. ### Claim 15 An apparatus, comprising: means for receiving, by an artificial neural network, an input; means for mapping the input to a multiple row input based at least in part on a processing capacity of a compute device; means for performing, by the compute device, concurrent convolution operations according to the multiple row input; and means for generating an output based on the concurrent convolution operations. ### Claim 16 (depends on 15) The apparatus of claim 15, in which the input comprises a one-dimensional tensor or a multi-dimensional tensor. ### Claim 17 (depends on 15) The apparatus of claim 15, further comprising means for computing, by a multiply-accumulate (MAC) unit of a neural processing unit, the concurrent convolution operations according to the multiple row input. ### Claim 18 (depends on 15) The apparatus of claim 15, further comprising means for mapping the input into the multiple row input by adapting fetching of the input from memory. ### Claim 19 (depends on 15) The apparatus of claim 15, in which the input includes hardware padding before a first element of the input or after a last element of the input. ### Claim 20 (depends on 19) The apparatus of claim 19, further comprising: means for splitting the input into multiple portions; means for remapping a first portion of the input without the hardware padding into the multiple row input; and means for processing a second portion of the input, the second portion including the hardware padding, without mapping the second portion to the multiple row input.