# US 2026/0093643 A1 · Quad-channel dram > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093643 A1 - Document ID: US20260093643A1 - Status: Published application - Kind: A1 - Application number: 19/258,624 - Filed: 2025-07-02 - Published: 2026-04-02 - Earliest claimed: 2019-02-28 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Steven C. WOO; Torsten PARTSCH - Web page: https://patentgrep.com/patent/US20260093643A1 ## CPC - G06F 13/1668: {Details of memory controller} - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/1045: {Read-write mode select circuits} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G11C 2207/105: Aspects related to pads, pins or terminals - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces. ## Claims ### Claim 1 (canceled) ### Claim 2 A memory controller integrated circuit operable in a first mode or a second mode, the memory controller integrated circuit comprising: first and second channel interfaces, wherein in the first mode, the first and second channel interfaces are configured to send commands, and transfer data, via respective first and second memory channels of a first DRAM device; third and fourth channel interfaces, wherein in the first mode, the third and fourth channel interfaces are configured to send commands, and transfer data, via respective first and second memory channels of a second DRAM device; and in the second mode, each of the first, second, third, and fourth channel interfaces are configured to send commands, and transfer data, via respective first, second, third, and fourth memory channels of a third DRAM device. ### Claim 3 (depends on 2) The memory controller integrated circuit of claim 2, wherein one or more of the first, second, third, and fourth channel interfaces is to provide configuration information to specify the first mode or the second mode. ### Claim 4 (depends on 3) The memory controller integrated circuit of claim 3, wherein the configuration information is specified by the memory controller integrated circuit asserting a voltage on a pin of one or more of the first, second, or third DRAM devices, during a power-up operating state. ### Claim 5 (depends on 3) The memory controller integrated circuit of claim 3, wherein the configuration information is specified by a value transmitted by the memory controller integrated circuit to the first and second DRAM devices, wherein the value specifies a clamshell top-side bottom-side configuration in the first mode. ### Claim 6 (depends on 3) The memory controller integrated circuit of claim 3, wherein the first mode is suitable to support a clamshell configuration for the first and second DRAM devices, such that the first and second DRAM devices are suited to be mounted on opposite sides of a substrate that includes the memory controller integrated circuit. ### Claim 7 (depends on 6) The memory controller integrated circuit of claim 6, wherein the clamshell configuration is a top-side/bottom side mode specified by the configuration information. ### Claim 8 (depends on 2) The memory controller integrated circuit of claim 2, wherein each channel interface of the first, second, third and fourth channel interfaces comprises independent first interface circuitry for transmitting command and address information, second interface circuitry for transferring data, and third interface circuitry for transmitting a clock signal. ### Claim 9 A memory controller integrated circuit, comprising: a plurality of command/address (CA) interfaces to transmit configuration information to one or more dynamic random access memory (DRAM) devices, the configuration information to specify a first mode or a second mode, wherein: in the first mode, a first and second CA interface of the plurality of CA interfaces is assigned to a first connection site for mounting a first DRAM device, and a third and a fourth CA interface of the plurality of CA interfaces is assigned to a second connection site for mounting a second DRAM device; and in the second mode, each of the first, second, third, and fourth CA interfaces are respectively assigned to a third connection site for mounting a third DRAM device. ### Claim 10 (depends on 9) The memory controller integrated circuit of claim 9, further comprising a plurality of data interfaces, wherein each CA interface of the plurality of CA interfaces includes a corresponding data interface of the plurality of data interfaces, wherein each data interface is assigned to a respective quadrant of the third connection site in the second mode. ### Claim 11 (depends on 10) The memory controller integrated circuit of claim 10, wherein, in the first mode a first two of the plurality of data interfaces are assigned to the first connection site and a second two of the plurality of data interfaces are assigned to the second connection site, and wherein the second connection site and the third connection site are disposed at the same location of a substrate. ### Claim 12 (depends on 9) The memory controller integrated circuit of claim 9, further comprising a plurality of clock signal interfaces, wherein each CA interface of the plurality of CA interfaces includes a corresponding clock signal interface of the plurality of clock signal interfaces, wherein each clock signal interface is assigned to a respective quadrant of the third connection site in the second mode. ### Claim 13 (depends on 12) The memory controller integrated circuit of claim 12, wherein, in the first mode a first two of the plurality of clock signal interfaces are assigned to the first connection site and a second two of the plurality of clock signal interfaces are assigned to the second connection site. ### Claim 14 (depends on 9) The memory controller integrated circuit of claim 9, wherein each of the first, second and third connection sites are assigned connection locations on a substrate that includes the memory controller integrated circuit. ### Claim 15 (depends on 9) The memory controller integrated circuit of claim 9, wherein the first mode supports a clamshell configuration having the first DRAM device mounted on a top-side of a substrate and the second DRAM device mounted on a bottom-side of the substrate. ### Claim 16 An electronic assembly comprising: a substrate having signal routing coupled to connection locations, each configured for mounting a dynamic random access memory (DRAM) device, each connection location having quadrants for interfacing with respective memory channels of the DRAM device; and a memory controller integrated circuit operable in a first mode or a second mode, the memory controller integrated circuit comprising: first and second command/address (CA) interfaces, wherein in the first mode, the first and second CA interfaces are configured to provide signals to respective first and second quadrants on a first side of the substrate; third and fourth CA interfaces, wherein in the first mode, the third and fourth CA interfaces are configured to provide signals to respective first and second quadrants of a second side of the substrate; and in the second mode, each of the first, second, third, and fourth CA interfaces are configured to provide signals to respective first, second, third, and fourth quadrants of a single connection location. ### Claim 17 (depends on 16) The electronic assembly of claim 16, wherein the memory controller integrated circuit further comprises a plurality of data interfaces, wherein each respective memory channel interfaced to the first, second, third, and fourth command/address interfaces include a respective corresponding data interface of the plurality of data interfaces. ### Claim 18 (depends on 16) The electronic assembly of claim 16, wherein each connection location having quadrants is configured as a rectangular array of solder ball reception locations divided by perpendicular axes into four quadrants. ### Claim 19 (depends on 16) The electronic assembly of claim 16, wherein one or more of the first, second, third, and fourth CA interfaces is to provide configuration information to specify the first mode or the second mode. ### Claim 20 (depends on 19) The electronic assembly of claim 19, wherein the configuration information is specified by the memory controller integrated circuit asserting a voltage on a pin of at least one of a first DRAM device and second DRAM device during a power-up operating state. ### Claim 21 (depends on 20) The electronic assembly of claim 20 wherein the configuration information specifies a top-side/bottom-side mode as the first mode if the voltage asserted by the memory controller integrated circuit is a first state during the power up of at least one of the first DRAM device and the second DRAM device.