Staggering self-refresh operations in memory systems

A method for operating a memory system, comprising:

• receiving a self-refresh entry command at an interface memory die of a stack of memory dies, the stack of memory dies comprising at least one memory die stacked on the interface memory die;
• enabling, by the interface memory die, a self-refresh enable signal to the at least one memory die in response to receiving the self-refresh entry command;
• performing a first internal refresh operation at the interface memory die in accordance with the self-refresh enable signal being enabled and a first counter associated with the interface memory die;
• and
• performing, a second internal refresh operation at the at least one memory die in accordance with the self-refresh enable signal being enabled and a second counter associated with the at least one memory die, wherein the second internal refresh operation is staggered from the first internal refresh operation in time in accordance with the first counter being offset from the second counter.

A memory system, comprising:

• a stack of memory dies comprising an interface memory die and at least one memory die stacked on the interface memory die, the interface memory die and the at least one memory die configured to have identification signals different from each other, respectively, wherein the stack of memory dies is configured to:
• receive a self-refresh entry command at the interface memory die;
• perform a first internal refresh operation at the interface memory die based, at least in part, on the self-refresh entry command and the identification signal of the interface memory die;
• and
• perform a second internal refresh operation at the at least one memory die based, at least in part, on the self-refresh entry command and the identification signal of the at least one memory die;
• wherein the second internal refresh operation is staggered from the first internal refresh operation in time based, at least in part, on a difference between the identification signals of the interface memory die and the at least one memory die.