# US 2026/0093618 A1 · Memory controller with oversampling memory i/o

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- Number: US 2026/0093618 A1
- Document ID: US20260093618A1
- Status: Published application
- Kind: A1
- Application number: 19/337,063
- Filed: 2025-09-23
- Published: 2026-04-02
- Earliest claimed: 2024-10-02
- Assignees: Mediatek Inc.
- Applicants: MediaTek Inc.
- Inventors: Arvind Kumar; Mahesh K. Kumashikar; Ankireddy Nalamalpu
- Web page: https://patentgrep.com/patent/US20260093618A1

## CPC

- G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G06F 13/1668: {Details of memory controller}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- H04L 25/4917: {using multilevel codes}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A memory controller in an integrated circuit system includes a receiver circuit that performs oversampling in time and voltage. The receiver circuit receives a data signal with pulse amplitude modulation (PAM) having N signal levels from a memory module over a data lane, N > 2. The receiver circuit generates K samples by sampling the data signal at a sequence of time points in a unit time interval. The receiver circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample out of the K samples. The voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks. The receiver circuit identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

## Claims

### Claim 1

A method of a receiver circuit in a memory controller in an integrated circuit system, comprising:
receiving a data signal modulated with pulse amplitude modulation (PAM) having N signal levels from a memory module in the integrated circuit system over a data lane, N being an integer greater than 2;
generating K samples by sampling the data signal at a sequence of time points in a unit time interval, K being an in-phase oversampling factor;
generating R signal level estimates from a same one of the K samples by R voltage comparator blocks, wherein the R voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks, and R is a quadrature-phase oversampling factor;
identifying one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples; and
outputting a symbol corresponding to the identified signal level.

### Claim 2 (depends on 1)

The method of claim 1, wherein generating the R signal level estimates further comprises:
generating K sets of R signal level estimates from the K samples; and
producing a total of (K x R) signal level estimates in the unit time interval.

### Claim 3 (depends on 1)

The method of claim 1, wherein identifying one of the N signal levels further comprises:
identifying the one signal level that is the most repeated among the all signal level estimates.

### Claim 4 (depends on 1)

The method of claim 1, wherein identifying one of the N signal levels further comprises:
calculating an average of the all signal level estimates; and
identifying the one signal level that is equal to or the closest to the average among the all signal level estimates.

### Claim 5 (depends on 1)

The method of claim 1, wherein identifying one of the N signal levels further comprises:
assigning a weight to each of the all signal level estimates;
calculating a weighted average of the all signal level estimates; and
identifying the one signal level that is equal to or the closest to the weighted average among the all signal level estimates.

### Claim 6 (depends on 1)

The method of claim 1, wherein the offsets and spacing of the time points are programmable.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
receiving an indication of signal quality of received signals; and
activating or deactivating one or more of samplers that sample the K samples to increase or decrease the in-phase oversampling factor K based on the signal quality.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
receiving an indication of signal quality of received signals; and
activating or deactivating one or more of the R voltage comparator blocks to increase or decrease the quadrature oversampling factor R based on the signal quality.

### Claim 9 (depends on 1)

The method of claim 1, wherein the data signal is modulated with PAM-8.

### Claim 10 (depends on 1)

The method of claim 1, wherein the data signal is modulated with PAM-16.

### Claim 11

A memory controller in an integrated circuit system, comprising:
a transmitter module to send outgoing data to a memory module in the integrated circuit system; and
a receiver module including a plurality of receiver circuits to receive incoming data modulated with pulse amplitude modulation (PAM) having N signal levels from the memory module over a plurality of data lanes, N being an integer greater than 2, each receiver circuit including:
a plurality of (K) samplers that sample a data signal received on a data lane at a sequence of time points in a unit time interval to generate K samples, K being an in-phase oversampling factor;
a plurality of (K) signal level detectors to receive the K samples, respectively, wherein each signal level detector includes a plurality of (R) voltage comparator blocks and R is a quadrature-phase oversampling factor, and wherein the R voltage comparator blocks are operative to compare a same one of the K samples against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks to thereby generate R signal level estimates; and
a decision circuit that identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein the K signal level detectors are further operative to:
generate K sets of R signal level estimates from the K samples; and
produce a total of (K x R) signal level estimates in the unit time interval.

### Claim 13 (depends on 11)

The memory controller of claim 11, wherein the decision circuit is further operative to:
identify the one signal level that is the most repeated among the all signal level estimates.

### Claim 14 (depends on 11)

The memory controller of claim 11, wherein the decision circuit is further operative to:
calculate an average of the all signal level estimates; and
identify the one signal level that is equal to or the closest to the average among the all signal level estimates.

### Claim 15 (depends on 11)

The memory controller of claim 11, wherein the decision circuit is further operative to:
assign a weight to each of the all signal level estimates;
calculate a weighted average of the all signal level estimates; and
identify the one signal level that is equal to or the closest to the weighted average among the all signal level estimates.

### Claim 16 (depends on 11)

The memory controller of claim 11, wherein the offsets and spacing of the time points are programmable.

### Claim 17 (depends on 11)

The memory controller of claim 11, further comprising:
a signal quality detector to detect signal quality of received signals; and
an oversampling control circuit to activate or deactivate one or more of the K samplers to increase or decrease the in-phase oversampling factor K based on the signal quality.

### Claim 18 (depends on 17)

The memory controller of claim 17, wherein the signal quality is indicated by a voltage noise level in the data signal.

### Claim 19 (depends on 11)

The memory controller of claim 11, further comprising:
a signal quality detector to detect signal quality of received signals; and
an oversampling control circuit to activate or deactivate one or more of the R voltage comparator blocks in each signal level detector to increase or decrease the quadrature oversampling factor R based on the signal quality.

### Claim 20 (depends on 19)

The memory controller of claim 19, wherein the signal quality is indicated by a timing noise level in a timing signal accompanying the data signal.