# US 2026/0093578 A1 · Data processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093578 A1 - Document ID: US20260093578A1 - Status: Published application - Kind: A1 - Application number: 18/899,342 - Filed: 2024-09-27 - Published: 2026-04-02 - Earliest claimed: 2024-09-27 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Daren Croxford; Jussi Tuomas Pennala; Philip Malcolm Done; Mark Stephen Bellamy - Web page: https://patentgrep.com/patent/US20260093578A1 ## CPC - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 12/023: {Free address space management} - G06F 13/1668: {Details of memory controller} - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed. ## Claims ### Claim 1 An apparatus comprising: a memory element, wherein the memory element comprises an access lane, wherein the access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the access lane of the memory element together with the set of data bits for which the error checking bits are implementing the memory error checking scheme, and wherein the access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the access lane; and an associated memory interface circuit including memory access logic for controlling access to the respective memory element, wherein, when new data is to be written to a sub-portion of the access lane, the memory access logic is selectively controllable to perform different memory access operations, including: i. a first access operation comprising reading the full data width of the access lane, thus including reading all of the data bits and the corresponding error checking bits, and then writing the new data into the full data width of the access lane together with an updated set of error checking bits based on the new data; and ii. a second, different access operation in which the new data can be written to a selected one or more of the channels of the set of plural channels into which the access lane is configured. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the access lane has a data width greater than 16 bits. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the access lane has a data width greater than 32 bits. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the number of data bits stored within the access lane is at least twice the number of error checking bits stored within the access lane. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the set of error checking bits includes a plurality of error checking bits, and wherein the access lane is configured such that the plurality of error checking bits are distributed across the set of plural of channels into which the access lane is configured, each channel thus respectively operable to store both data bits and a respective one or more error checking bits from the set of error checking bits. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the set of error checking bits includes a plurality of error checking bits, and wherein the access lane is configured such that the respective set of error checking bits is stored in a respective one of the channels into which the access lane is configured. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the first access operation is performed as a read-modify write operation. ### Claim 8 A data processing system comprising: at least one processing element; a respective memory element that the at least one processing element is operable to access when performing its processing, wherein the memory element comprises an access lane, wherein the access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the access lane together with the set of data bits for which the error checking bits are implementing the memory error checking scheme, and wherein the access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the access lane; and an associated memory interface circuit including memory access logic for controlling the at least one processing element's access to the respective memory element, wherein the memory error checking scheme can be selectively enabled in respect of the memory element, and wherein, when new data is to be written to a sub-portion of the access lane, the memory access logic is configured to perform different memory access operations depending on whether or not the memory error checking scheme is enabled, wherein: when the memory error checking scheme is enabled, the memory access logic is configured to perform a first access operation comprising reading the full data width of the access lane, thus including reading all of the data bits and the corresponding error checking bits, and then writing the new data into the full data width of the access lane together with an updated set of error checking bits based on the new data, whereas when the memory error checking scheme is not enabled, the memory access logic is operable to perform a second, different access operation in which the new data can be written to a selected one or more of the channels of the set of plural channels into which the access lane is configured. ### Claim 9 (depends on 8) The data processing system of claim 8, wherein the respective memory element has a data width greater than 16 bits. ### Claim 10 (depends on 9) The data processing system of claim 9, wherein the respective memory element has a data width greater than 32 bits. ### Claim 11 (depends on 8) The data processing system of claim 8, wherein the number of data bits stored within the access lane is at least twice the number of error checking bits stored within the access lane. ### Claim 12 (depends on 8) The data processing system of claim 8, wherein the set of error checking bits includes a plurality of error checking bits, and wherein the memory element is configured such that the plurality of error checking bits are distributed across the set of plural of channels into which the access lane is configured, each channel thus respectively operable to store both data bits and a respective one or more error checking bits from the set of error checking bits. ### Claim 13 (depends on 8) The data processing system of claim 8, wherein the set of error checking bits includes a plurality of error checking bits, and wherein the access lane is configured such that the respective set of error checking bits is stored in a respective one of the channels into which the access lane is configured. ### Claim 14 (depends on 8) The data processing system of claim 8, wherein the first access operation is performed as a read-modify write operation. ### Claim 15 (depends on 8) The data processing system of claim 8, wherein when data is to be read from the respective access lane, when the memory error checking scheme is enabled, the memory access logic is configured to issue a read transaction to read the full data width of the access lane, whereas when the memory error checking scheme is not enabled, the memory access logic is configured to issue a read transaction to read only the desired data bits. ### Claim 16 (depends on 8) The data processing system claim 8, wherein the at least one processing unit is a graphics processor or a processing unit within a graphics processor. ### Claim 17 (depends on 8) The data processing system of claim 8, wherein the memory error checking scheme can be selectively enabled in respect of the memory element on a per-output basis. ### Claim 18 A method of initialising a memory element access lane for subsequent memory accesses, wherein the memory element access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the memory element access lane together with the set of data bits for which the error checking bits are implementing the memory error checking scheme, wherein the memory error checking scheme can be selectively enabled in respect of the memory element, and wherein the method comprises: when the memory error checking scheme is not enabled in respect of the memory element: setting the value of each of the error checking bits in the set of error checking bits to a same value, the same value being whichever of 0 or 1 it is more efficient to read from the memory element access lane. ### Claim 19 (depends on 18) The method of claim 18, wherein the memory element access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the memory element access lane, and wherein the set of error checking bits includes a plurality of error checking bits that are distributed across the set of plural of channels into which the memory element access lane is configured, each channel thus respectively operable to store both data bits and a respective one or more error checking bits from the set of error checking bits, the method comprising: when the memory error checking scheme is not enabled in respect of the memory element: whenever data is to be written to a particular one of the channels into which the memory element access lane is configured, writing the said same value for each of the error checking bits stored within that channel. ### Claim 20 (depends on 18) The method of claim 18, wherein the memory element access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the memory element access lane, and wherein the set of error checking bits includes a plurality of error checking bits that are stored within a respective one of the channels into which the memory element access lane is configured, the method comprising: when the memory error checking scheme is not enabled in respect of the memory element: initially setting the value of each of the error checking bits in the set of error checking bits to said same value; and then controlling subsequent writes such that the respective one of the channels that stores the error checking bits is not written to.