# US 2026/0093577 A1 · Controller and memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093577 A1 - Document ID: US20260093577A1 - Status: Published application - Kind: A1 - Application number: 19/039,156 - Filed: 2025-01-28 - Published: 2026-04-02 - Earliest claimed: 2024-10-02 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Chang Hyun PARK - Web page: https://patentgrep.com/patent/US20260093577A1 ## CPC - G06F 11/1016: {Error in accessing a memory location, i.e. addressing error} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1441: {Resetting or repowering} - G06F 11/273: Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In embodiments of the present disclosure, when a memory which has a defect (failed memory) occurs in a memory system including a plurality of memories, detect read operations are performed in a state in which each of the plurality of memories is sequentially excluded in rotation, and a read operation is controlled by setting a memory which is excluded in a case where the number of corrected errors is smallest during the detect read operations, as an error memory. Therefore, a failed memory may be accurately detected, and even when a failed memory occurs among the plurality of memories, error correction performance may be improved to improve the operational performance of the memory system. ## Claims ### Claim 1 A memory system comprising: a plurality of memories; and a controller configured to perform a data read operation of reading data having a unit size from each of the plurality of memories, perform, when an uncorrectable error occurs during the data read operation, detect read operations, each detect read operation reading data having the unit size from each of remaining memories excluding at least one memory selected in rotation among the plurality of memories, check numbers of errors corrected in each of the detect read operations, and set, as an error memory, at least one memory excluded in a detect read operation in which a smallest number of errors is corrected, among the detect read operations. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the controller is configured to set a value of a background test register to a first value when the error memory is set, and perform a test read operation on the error memory. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the controller is configured to: perform, during a period in which the value of the background test register is set to the first value, the data read operation on remaining memories excluding the error memory among the plurality of memories; and reset an error memory when the uncorrectable error occurs in the data read operation. ### Claim 4 (depends on 2) The memory system according to claim 2, wherein the controller is configured to reset an error memory when a number of errors detected in the test read operation is smaller than a preset number. ### Claim 5 (depends on 2) The memory system according to claim 2, wherein when a number of errors detected in the test read operation is equal to or greater than a preset number are, the controller is configured to set the value of the background test register to a second value without performing the test read operation. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein the controller is configured to: perform, during a period in which the value of the background test register is set to the second value, the data read operation on remaining memories excluding the error memory among the plurality of memories; and skip an operation of searching for an error memory when the uncorrectable error occurs in the data read operation. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein when the uncorrectable error occurs in the data read operation for the plurality of memories, the controller is configured to: perform a first detect read operation on remaining memories excluding a first memory among the plurality of memories; and perform a second detect read operation on remaining memories excluding a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when the uncorrectable error does not occur in the first detect read operation and the second detect read operation. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein the number of errors corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation. ### Claim 9 (depends on 7) The memory system according to claim 7, wherein when a number of errors corrected in the first detect read operation and a number errors corrected in the second detect read operation are identical to each other and corresponds to the smallest number of errors, the controller is configured to notify an external device of that the uncorrectable error has occurred. ### Claim 10 (depends on 1) The memory system according to claim 1, wherein when the error memory is set, the controller is configured to perform the data read operation on the remaining memories excluding the error memory among the plurality of memories. ### Claim 11 (depends on 1) The memory system according to claim 1, wherein when the error memory is set, the controller is configured to transmit an error memory setting notification signal to an external device. ### Claim 12 (depends on 1) The memory system according to claim 1, wherein data read from the plurality of memories includes user data, metadata and parity data, and wherein a size of the parity data is smaller than two times the unit size. ### Claim 13 A memory system comprising: a plurality of memories; and a controller configured to perform a data read operation on remaining memories excluding an error memory, among the plurality of memories, perform a test read operation on the error memory, and sequentially perform detect read operations on memories other than one memory selected in rotation among the plurality of memories when a number of errors detected in the test read operation is smaller than a preset number. ### Claim 14 (depends on 13) The memory system according to claim 13, wherein the controller is configured to skip performing the detect read operations on the error memory. ### Claim 15 (depends on 13) The memory system according to claim 13, wherein the controller is configured to: perform a first detect read operation on memories other than a first memory among the plurality of memories; perform a second detect read operation on memories other than a second memory among the plurality of memories, and compares a number of errors corrected in the first detect read operation with a number of errors corrected in the second detect read operation when an uncorrectable error does not occur in the first detect read operation and the second detect read operation. ### Claim 16 (depends on 15) The memory system according to claim 15, wherein the number of error corrected in the first detect read operation is different from the number of errors corrected in the second detect read operation. ### Claim 17 (depends on 15) The memory system according to claim 15, wherein when the number of errors corrected in the first detect read operation is smaller than the number of errors corrected in the second detect read operation, the controller is configured to set the first memory as a new error memory, and perform the data read operation on the memories other than the first memory. ### Claim 18 (depends on 16) The memory system according to claim 16, wherein the number of errors corrected in the first detect read operation is smallest among numbers of errors corrected in each of the detect read operations. ### Claim 19 A controller comprising: a control circuit configured to perform a first read operation on a plurality of memories; and an error correction circuit configured to correct an error which occurs in the first read operation, wherein the control circuit is configured to: sequentially perform second read operations on memories excluding at least one memory selected in rotation among the plurality of memories when an uncorrectable error occurs in the first read operation, and set, as an error memory, a memory which is excluded in a second read operation in which a smallest number of errors is corrected, among the second read operations. ### Claim 20 (depends on 19) The controller according to claim 19, wherein the control circuit is configured to perform the first read operation on memories excluding the error memory among the plurality of memories, and perform a third read operation on the error memory.