# US 2026/0093576 A1 · Error detection and correction

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- Number: US 2026/0093576 A1
- Document ID: US20260093576A1
- Status: Published application
- Kind: A1
- Application number: 19/335,606
- Filed: 2025-09-22
- Published: 2026-04-02
- Earliest claimed: 2024-09-27
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Fabrice ROMAIN
- Web page: https://patentgrep.com/patent/US20260093576A1

## CPC

- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of detecting and correcting an error on at least two bits of a binary piece of data stored in a memory includes the following successive steps: (a) modifying a value of a bit of said binary piece of data; (b) implementing a mechanism for correcting an error on a bit of said modified binary piece of data; and (c) if a fault is still detected, repeating step (a) by modifying the value of another bit of said binary piece of data.

## Claims

### Claim 1

A method of detecting and correcting an error on at least two bits of a binary piece of data stored in a memory, comprising the following successive steps:
(a) modifying a value of a bit of said binary piece of data to produce a modified binary piece of data;
(b) implementing a mechanism for correcting an error on a bit of said modified binary piece of data;
(c) when an error is still detected, repeating step (a) by modifying the value of another bit of said binary piece of data and then performing step (b).

### Claim 2 (depends on 1)

The method according to claim 1, further comprising, after step (b) and where no fault is detected after implementing the mechanism for correcting, d) making the value of said binary piece of data equal to the value of said modified binary piece of data, and considering the error corrected.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising, prior to step (a), (e) implementing said mechanism for correcting an error on a bit of said binary piece of data.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising, after step (e), and where no fault is detected after implementing the mechanism for correcting, f) making the value of said binary piece of data equal to the value of said binary piece of data obtained at step (e), and considering the error corrected.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising, after step (c), and where all the bit values of said binary piece of data have been modified at least once and a fault is still detected, g) considering said binary piece of data to be uncorrectable.

### Claim 6 (depends on 1)

The method according to claim 1, wherein said mechanism of correction of an error on a bit uses a Hamming code.

### Claim 7 (depends on 1)

The method according to claim 1, wherein said binary piece of data comprises bits representing an error detection and correction code and bits representing a value of said binary piece of data.

### Claim 8 (depends on 7)

The method according to claim 7, wherein said mechanism of correction of an error on a bit comprises calculation of a piece of data of comparison of said detection and correction code and a code recalculated from said value of said binary piece of data.

### Claim 9 (depends on 7)

The method according to claim 7, wherein said mechanism of correction comprises circuitry for automatically calculating a corrected error detection and correction code.

### Claim 10 (depends on 1)

A device for detecting and correcting an error on at least two bits of a binary piece of data stored in a memory, configured to implement the method of claim 1.