# US 2026/0093546 A1 · Method and apparatus for scheduling virtual machine thread > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093546 A1 - Document ID: US20260093546A1 - Status: Published application - Kind: A1 - Application number: 19/293,301 - Filed: 2025-08-07 - Published: 2026-04-02 - Earliest claimed: 2024-09-30 - Applicants: Beijing Volcano Engine Technology Co., Ltd. - Inventors: Zhimin Feng - Web page: https://patentgrep.com/patent/US20260093546A1 ## CPC - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5033: {considering data affinity} - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/5044: {considering hardware capabilities} - G06F 9/505: {considering the load} - G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)} - G06F 2009/4557: {Distribution of virtual machine instances; Migration and load balancing} - G06F 2209/486: Scheduler internals - G06F 2209/5014: Reservation - G06F 2209/5018: Thread allocation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments of the present disclosure provide a method and an apparatus for scheduling a virtual machine thread includes: determining, by a load balancing scheduler, processor affinity of a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine in response to receiving a scheduling instruction for the first VCPU thread; determining, based on the processor affinity of the first VCPU thread, a second hyper-threading logical processor in the target physical processor as processor affinity of a second VCPU thread in the virtual processor; scheduling, based on the processor affinity of the first VCPU thread, the first hyper-threading logical processor to run the first VCPU thread; and scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ## Claims ### Claim 1 A method for scheduling a virtual machine thread, comprising: determining, by a load balancing scheduler, processor affinity of a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine in response to receiving a scheduling instruction for the first VCPU thread, wherein the processor affinity of the first VCPU thread is used to configure a first hyper-threading logical processor running the first VCPU thread and a target physical processor to which the first hyper-threading logical processor belongs; determining, based on the processor affinity of the first VCPU thread, a second hyper-threading logical processor in the target physical processor as processor affinity of a second VCPU thread in the virtual processor; and scheduling, based on the processor affinity of the first VCPU thread, the first hyper-threading logical processor to run the first VCPU thread, and scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 2 (depends on 1) The method of claim 1, wherein a thread number of the first VCPU thread and a thread number of the second VCPU thread have different parity. ### Claim 3 (depends on 1) The method of claim 1, wherein, before scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread, the method further comprises: determining an operating status of the second VCPU thread on the virtual processor; and in response to the operating status of the second VCPU thread being a running status, scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 4 (depends on 1) The method of claim 1, wherein the virtual machine comprises a plurality of virtual processors each running two VCPU threads; and correspondingly, the method further comprises: obtaining operating statuses of the two VCPU threads being run on each virtual processor; and in response that one VCPU thread on a same virtual processor is in a running status and occupies one hyper-threading logical processor of the physical processor and the other VCPU thread on the same virtual processor is in a blocked status, waking up the other VCPU thread in the blocked status and preempting a further hyper-threading logical processor of the physical processor. ### Claim 5 (depends on 4) The method of claim 4, wherein waking up the other VCPU thread in the blocked status and preempting the further hyper-threading logical processor of the physical processor comprises: sending a wake-up instruction to the other VCPU thread in the blocked status to wake up the other VCPU thread in the blocked status, and enabling the woken-up VCPU thread to execute a processor wait (mwait) instruction to preempt the further hyper-threading logical processor of the physical processor, wherein the mwait instruction is used to enable the VCPU thread to be in a low power consumption mode. ### Claim 6 (depends on 4) The method of claim 4, further comprising: controlling the other VCPU thread to stop executing the mwait instruction and switch to the blocked status in response that the operating status of the one VCPU thread on the same virtual processor is switched from the running status to the blocked status. ### Claim 7 (depends on 1) The method of claim 1, wherein determining, by the load balancing scheduler, processor affinity of the first VCPU thread on the virtual processor of the virtual machine in response to receiving the scheduling instruction for the first VCPU thread comprises: determining, by the load balancing scheduler, a target physical processor with a minimum load from a plurality of candidate physical processors in response to receiving the scheduling instruction for the first VCPU thread on the virtual processor of the virtual machine; and determining the first hyper-threading logical processor in the target physical processor with the minimum load as the processor affinity of the first VCPU thread. ### Claim 8 An electronic device, comprising: a processor, and a memory, wherein the memory stores computer-executable instructions; and the processor executes the computer-executable instructions stored in the memory to cause the processor to: determine processor affinity of a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine in response to receiving a scheduling instruction for the first VCPU thread, wherein the processor affinity of the first VCPU thread is used to configure a first hyper-threading logical processor running the first VCPU thread and a target physical processor to which the first hyper-threading logical processor belongs; determine, based on the processor affinity of the first VCPU thread, a second hyper-threading logical processor in the target physical processor as processor affinity of a second VCPU thread in the virtual processor; and schedule, based on the processor affinity of the first VCPU thread, the first hyper-threading logical processor to run the first VCPU thread, and schedule, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein a thread number of the first VCPU thread and a thread number of the second VCPU thread have different parity. ### Claim 10 (depends on 8) The electronic device of claim 8, wherein, before scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread, the computer-executable instructions further cause the processor to: determine an operating status of the second VCPU thread on the virtual processor; and in response to the operating status of the second VCPU thread being a running status, schedule, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 11 (depends on 8) The electronic device of claim 8, wherein the virtual machine comprises a plurality of virtual processors each running two VCPU threads; and the computer-executable instructions further cause the processor to: obtain operating statuses of the two VCPU threads being run on each virtual processor; and in response that one VCPU thread on a same virtual processor is in a running status and occupies one hyper-threading logical processor of the physical processor and the other VCPU thread on the same virtual processor is in a blocked status, wake up the other VCPU thread in the blocked status and preempt a further hyper-threading logical processor of the physical processor. ### Claim 12 (depends on 11) The electronic device of claim 11, wherein the computer-executable instructions configured to wake up the other VCPU thread in the blocked status and preempt the further hyper-threading logical processor of the physical processor comprises instructions causing the processor to: send a wake-up instruction to the other VCPU thread in the blocked status to wake up the other VCPU thread in the blocked status, and enabling the woken-up VCPU thread to execute a processor wait (mwait) instruction to preempt the further hyper-threading logical processor of the physical processor, wherein the mwait instruction is used to enable the VCPU thread to be in a low power consumption mode. ### Claim 13 (depends on 11) The electronic device of claim 11, wherein the computer-executable instructions further cause the processor to: control the other VCPU thread to stop executing the mwait instruction and switch to the blocked status in response that the operating status of the one VCPU thread on the same virtual processor is switched from the running status to the blocked status. ### Claim 14 (depends on 8) The electronic device of claim 8, wherein the computer-executable instructions configured to determine processor affinity of the first VCPU thread on the virtual processor of the virtual machine in response to receiving the scheduling instruction for the first VCPU thread comprises instructions causing the processor to: determine a target physical processor with a minimum load from a plurality of candidate physical processors in response to receiving the scheduling instruction for the first VCPU thread on the virtual processor of the virtual machine; and determine the first hyper-threading logical processor in the target physical processor with the minimum load as the processor affinity of the first VCPU thread. ### Claim 15 A non-transitory computer-readable storage medium, storing computer-executable instructions which, when executed by a processor, cause the processor to: determine processor affinity of a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine in response to receiving a scheduling instruction for the first VCPU thread, wherein the processor affinity of the first VCPU thread is used to configure a first hyper-threading logical processor running the first VCPU thread and a target physical processor to which the first hyper-threading logical processor belongs; determine, based on the processor affinity of the first VCPU thread, a second hyper-threading logical processor in the target physical processor as processor affinity of a second VCPU thread in the virtual processor; and schedule, based on the processor affinity of the first VCPU thread, the first hyper-threading logical processor to run the first VCPU thread, and schedule, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 16 (depends on 15) The storage medium of claim 15, wherein a thread number of the first VCPU thread and a thread number of the second VCPU thread have different parity. ### Claim 17 (depends on 15) The storage medium of claim 15, wherein, before scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread, the computer-executable instructions further cause the processor to: determine an operating status of the second VCPU thread on the virtual processor; and in response to the operating status of the second VCPU thread being a running status, schedule, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread. ### Claim 18 (depends on 15) The storage medium of claim 15, wherein the virtual machine comprises a plurality of virtual processors each running two VCPU threads; and the computer-executable instructions further cause the processor to: obtain operating statuses of the two VCPU threads being run on each virtual processor; and in response that one VCPU thread on a same virtual processor is in a running status and occupies one hyper-threading logical processor of the physical processor and the other VCPU thread on the same virtual processor is in a blocked status, wake up the other VCPU thread in the blocked status and preempt a further hyper-threading logical processor of the physical processor. ### Claim 19 (depends on 18) The storage medium of claim 18, wherein the computer-executable instructions configured to wake up the other VCPU thread in the blocked status and preempt the further hyper-threading logical processor of the physical processor comprises instructions causing the processor to: send a wake-up instruction to the other VCPU thread in the blocked status to wake up the other VCPU thread in the blocked status, and enabling the woken-up VCPU thread to execute a processor wait (mwait) instruction to preempt the further hyper-threading logical processor of the physical processor, wherein the mwait instruction is used to enable the VCPU thread to be in a low power consumption mode. ### Claim 20 (depends on 18) The storage medium of claim 18, wherein the computer-executable instructions further cause the processor to: control the other VCPU thread to stop executing the mwait instruction and switch to the blocked status in response that the operating status of the one VCPU thread on the same virtual processor is switched from the running status to the blocked status.