# US 2026/0093501 A1 · Apparatus and method for dynamic microarchitecture adaption using machine learning to improve core performance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093501 A1 - Document ID: US20260093501A1 - Status: Published application - Kind: A1 - Application number: 18/900,524 - Filed: 2024-09-27 - Published: 2026-04-02 - Earliest claimed: 2024-09-27 - Inventors: Zhu Zhou; Bin Li; Gilles Pokam; Wessam Elhefnawy - Web page: https://patentgrep.com/patent/US20260093501A1 ## CPC - G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files} - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/045: Combinations of networks - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06N 3/092: Reinforcement learning - G06N 5/01: Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound - G06N 20/00: Machine learning - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract An apparatus and method for dynamic microarchitecture adaptation based on machine learning implementations. For example, one embodiment of a method comprises: configuring a trained reinforcement learning model on a machine learning circuitry integral to a first processor of a first processor type, the trained reinforcement learning model having been trained with microarchitectural performance data and workload data corresponding to the first processor type; determining, by the machine learning circuitry using the trained reinforcement learning model, microarchitectural configuration updates based on first telemetry data and characteristics of workloads to be executed; and applying the microarchitectural configuration updates on the first processor. ## Claims ### Claim 1 A method, comprising: configuring a trained reinforcement learning model on a machine learning circuitry integral to a first processor of a first processor type, the trained reinforcement learning model having been trained with microarchitectural performance data and workload data corresponding to the first processor type; determining, by the machine learning circuitry using the trained reinforcement learning model, microarchitectural configuration updates to be performed on a second processor based on first telemetry data and characteristics of workloads to be executed; and applying the microarchitectural configuration updates on the processor. ### Claim 2 (depends on 1) The method of claim 1, further comprising: evaluating, by the machine learning circuitry configured with the reinforcement learning model, second telemetry data associated with processing instructions on the second processor with the microarchitectural configuration updates; and performing additional training of the reinforcement learning model based on the second telemetry data. ### Claim 3 (depends on 2) The method of claim 2, further comprising: transforming the first telemetry data and the second telemetry data into a normalized format for the additional training of the reinforcement learning model. ### Claim 4 (depends on 1) The method of claim 1, wherein the reinforcement learning model is to implement temporal difference learning to attempt to maximize performance of the workloads. ### Claim 5 (depends on 4) The method of claim 4, wherein the temporal difference learning comprises Actor-Critic learning. ### Claim 6 (depends on 1) The method of claim 1, wherein the machine learning circuitry is configured to implement at least one policy neural network for performing inferencing operations to determine the microarchitectural configuration updates. ### Claim 7 (depends on 6) The method of claim 6, wherein the at least one policy neural network comprises multiple functional layers including: a first functional layer comprising performance counters to count specified microarchitectural events, telemetry collection circuitry of the first processor to collect values from the performance counters, and normalization circuitry to normalize the values; an N-layer neural network to receive the values as input, each layer comprising circuitry to implement connected neurons, layer normalization, and an activation function; and a final functional layer to implement a normalized exponential function to transform a vector of K real numbers provided by a layer of the N-layer neural network into a probability distribution of K possible outcomes. ### Claim 8 (depends on 7) The method of claim 7, wherein the machine learning circuitry is to perform the microarchitectural configuration updates based on the K possible outcomes. ### Claim 9 A processor, comprising: a plurality of microarchitectural circuits associated with processing instructions and data; machine learning circuitry configurable in accordance with a trained reinforcement learning model, the trained reinforcement learning model pre-trained based on a type of the processor; and telemetry collection circuitry to collect first telemetry data from the plurality of microarchitectural circuits or a subset thereof; wherein the machine learning circuitry operable in accordance with the trained reinforcement learning model is to determine microarchitectural configuration updates based on the first telemetry data and characteristics of at least one workload to be executed using one or more of the plurality of microarchitectural circuits. ### Claim 10 (depends on 9) The processor of claim 9, wherein the machine learning circuitry configured with the trained reinforcement learning model is to perform additional training of the trained reinforcement learning model based on second telemetry data collected following the microarchitectural configuration updates. ### Claim 11 (depends on 10) The processor of claim 10, wherein the machine learning circuitry further comprises normalization circuitry to transform the first telemetry data and the second telemetry data into a normalized format for determining the microarchitectural configuration updates and the additional training of the reinforcement learning model. ### Claim 12 (depends on 9) The processor of claim 9, wherein the reinforcement learning model is to implement temporal difference learning to attempt to maximize performance of the workloads. ### Claim 13 (depends on 12) The processor of claim 12, wherein the temporal difference learning comprises Actor-Critic learning. ### Claim 14 (depends on 9) The processor of claim 9, wherein the machine learning circuitry is to implement at least one policy neural network for inferencing operations, the inferencing operations to determine the microarchitectural configuration updates. ### Claim 15 (depends on 14) The processor of claim 14, wherein the at least one policy neural network comprises multiple functional layers including: a first functional layer comprising performance counters to count specified microarchitectural events, telemetry collection circuitry of the first processor to collect the first telemetry data and second telemetry data from the performance counters, and normalization circuitry to normalize the first telemetry data and second telemetry data to produce normalized data; an N-layer neural network to receive the normalized data as input, each layer comprising circuitry to implement connected neurons, layer normalization, and an activation function; and a final functional layer to implement a normalized exponential function to transform a vector of K real numbers provided by a layer of the N-layer neural network into a probability distribution of K possible outcomes. ### Claim 16 (depends on 15) The processor of claim 15, wherein the machine learning circuitry is to perform the microarchitectural configuration updates based on the K possible outcomes. ### Claim 17 A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations, comprising: configuring a trained reinforcement learning model on a machine learning circuitry integral to a first processor of a first processor type, the trained reinforcement learning model having been trained with microarchitectural performance data and workload data corresponding to the first processor type; determining, by the machine learning circuitry using the trained reinforcement learning model, microarchitectural configuration updates based on first telemetry data and characteristics of workloads to be executed; and applying the microarchitectural configuration updates on the first processor. ### Claim 18 (depends on 17) The machine-readable medium of claim 17, further comprising program code to cause the machine to perform the operations of: evaluating, by the machine learning circuitry configured with the reinforcement learning model, second telemetry data associated with the microarchitectural configuration updates; and performing additional training of the reinforcement learning model based on the second telemetry data. ### Claim 19 (depends on 18) The machine-readable medium of claim 18, further comprising program code to cause the machine to perform the operations of: transforming the first telemetry data and the second telemetry data into a normalized format for the additional training of the reinforcement learning model. ### Claim 20 (depends on 17) The machine-readable medium of claim 17, wherein the reinforcement learning model is to implement temporal difference learning to attempt to maximize performance of the workloads.