# US 2026/0093489 A1 · Vector floating-point flag update with micro-operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0093489 A1 - Document ID: US20260093489A1 - Status: Published application - Kind: A1 - Application number: 19/386,465 - Filed: 2025-11-12 - Published: 2026-04-02 - Earliest claimed: 2024-10-02 - Assignees: Akeana, Inc. - Applicants: Akeana, Inc. - Inventors: Abhijit Sil; Ricardo Ramirez - Web page: https://patentgrep.com/patent/US20260093489A1 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3004: {to perform operations on memory} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3455: {using stride} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector floating-point instructions and micro-operations. A vector floating-point instruction is decoded. The decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs). A reorder buffer assigns a reorder buffer ID (ROBID) to each of the one or more VFPMs, in which the assigning includes a micro-sequencer ID (MSID). The processor core executes the one or more VFPMs. The executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag. The architectural floating-point flag is set, based on the first update. The setting occurs after the one or more VFPMs have been committed by the processor core. A temporary floating-point flag is revised. The revising is based on the first update. ## Claims ### Claim 1 A processor-implemented method for vector processing comprising: accessing a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute vector floating-point instructions and micro-operations; decoding a vector floating-point instruction, wherein the decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs); assigning, by a reorder buffer (ROB), a reorder buffer ID (ROBID) to each of the one or more VFPMs, wherein the assigning includes a micro-sequencer ID (MSID); executing, by the processor core, the one or more VFPMs, wherein the executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag; and setting the architectural floating-point flag, wherein the setting is based on the first update, and wherein the setting occurs after the one or more VFPMs have been committed by the processor core. ### Claim 2 (depends on 1) The method of claim 1 wherein the setting includes revising a temporary floating-point flag, wherein the revising is based on the first update. ### Claim 3 (depends on 2) The method of claim 2 wherein the setting includes copying the temporary floating-point flag to the architectural floating-point flag. ### Claim 4 (depends on 3) The method of claim 3 wherein the requiring includes a second update by a second VFPM within the one or more VFPMs. ### Claim 5 (depends on 4) The method of claim 4 wherein the revising includes the second update. ### Claim 6 (depends on 1) The method of claim 1 further comprising checking, within the ROB, for availability for the one or more VFPMs, wherein the assigning is based on the checking. ### Claim 7 (depends on 6) The method of claim 6 wherein the ROB comprises a circular buffer. ### Claim 8 (depends on 7) The method of claim 7 wherein the ROB includes a wrap bit. ### Claim 9 (depends on 6) The method of claim 6 wherein the availability accommodates each VFPM in the one or more VFPMs. ### Claim 10 (depends on 6) The method of claim 6 wherein the availability does not accommodate each VFPM in the one or more VFPMs. ### Claim 11 (depends on 10) The method of claim 10 further comprising stalling the assigning of the one or more VFPMs. ### Claim 12 (depends on 1) The method of claim 1 wherein the MSID comprises the ROBID of a last VFPM within the one or more VFPMs. ### Claim 13 (depends on 1) The method of claim 1 wherein the vector floating-point instruction is associated with a vector length multiplier (VLM). ### Claim 14 (depends on 13) The method of claim 13 wherein each destination register of the one or more VFPMs is based on the VLM. ### Claim 15 (depends on 14) The method of claim 14 wherein the replacing is based on the one or more destination registers. ### Claim 16 (depends on 1) The method of claim 1 wherein the ROB is within a decode unit. ### Claim 17 (depends on 1) The method of claim 1 wherein the executing occurs out of order. ### Claim 18 (depends on 1) The method of claim 1 wherein the replacing is accomplished by a micro-operation sequencer. ### Claim 19 (depends on 1) The method of claim 1 wherein the setting is based on one or more control status registers (CSRs). ### Claim 20 A computer program product embodied in a non-transitory computer readable medium for vector processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic for: accessing a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute vector floating-point instructions and micro-operations; decoding a vector floating-point instruction, wherein the decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs); assigning, by a reorder buffer (ROB), a reorder buffer ID (ROBID) to each of the one or more VFPMs, wherein the assigning includes a micro-sequencer ID (MSID); executing, by the processor core, the one or more VFPMs, wherein the executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag; and setting the architectural floating-point flag, wherein the setting is based on the first update, and wherein the setting occurs after the one or more VFPMs have been committed by the processor core. ### Claim 21 A computer system for vector processing comprising: a memory which stores instructions; one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to: access a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute vector floating-point instructions and micro-operations; decode a vector floating-point instruction, wherein the decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs); assign, by a reorder buffer (ROB), a reorder buffer ID (ROBID) to each of the one or more VFPMs, wherein the assigning includes a micro-sequencer ID (MSID); execute, by the processor core, the one or more VFPMs, wherein the executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag; and set the architectural floating-point flag, wherein the setting is based on the first update, and wherein the setting occurs after the one or more VFPMs have been committed by the processor core.