Scandump simulation and co-simulation for device testing
AssigneeSamsung Electronics Co., Ltd.
InventorsChunlin WANG, Dongwoon KIM
Life of this patent
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Abstract
A system and a method for an integrated test circuit are described. The test circuit includes an interface circuit and a test controller. The interface circuit is configured to communicate with a device under test to obtain a test scandump from a scandump storage corresponding to an internal circuit of the device. The test controller is configured to generate a test sequence to the interface to control the device and enable a simulation performed by a simulator having a design associated with the device. The test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation. The mismatch pattern corresponds to a fault.
Claims20
A test circuit comprising:
- an interface circuit configured to communicate with a device under test to obtain a test scandump from a scandump storage corresponding to an internal circuit of the device;
- and
- a test controller configured to generate a test sequence to the interface circuit to control the device and enable a simulation performed by a simulator having a design associated with the device;
- wherein the test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation, the mismatch pattern corresponding to a fault.
A method comprising:
- communicating, by an interface circuit, with a device under test to obtain a test scandump from a scandump storage corresponding to an internal circuit of the device;
- and
- generating, by a test controller, a test sequence to the interface circuit to control the device and enabling a simulation performed by a simulator having a design associated with the device;
- wherein the test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation, the mismatch pattern corresponding to a fault.
A system comprising:
- a semiconductor device;
- and
- a test circuit to test the device, comprising:
- an interface circuit configured to communicate with the device to obtain a test scandump from a scandump storage corresponding to an internal circuit of the device;
- and
- a test controller configured to generate a test sequence to the interface circuit to control the device and enable a simulation performed by a simulator having a design associated with the device;
- wherein the test sequence includes identifying a mismatch pattern between a final scan pattern from a final scandump and a simulation pattern from the simulation, the mismatch pattern corresponding to a fault.
Dependencies are inferred from the claim text.