# US 2026/0090482 A1 · Power module package

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- Number: US 2026/0090482 A1
- Document ID: US20260090482A1
- Status: Published application
- Kind: A1
- Application number: 18/896,813
- Filed: 2024-09-25
- Published: 2026-03-26
- Earliest claimed: 2024-09-25
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Hangil SHIN; Jihwan KIM; Taekyun KIM; Seungwon IM
- Web page: https://patentgrep.com/patent/US20260090482A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 76/60: Seals
- H01R 12/585: {Terminals having a press fit or a compliant portion and a shank passing through a hole in the printed circuit board}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/00: Package configurations
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electronic power module is disclosed that forms external electrical connections without the use of a lead frame. Instead, various types of external connectors can be used, such as a press-fit pin assembly and an integrated connection post and power tap. Different methods of securing the external connectors to a multilayer substrate are also disclosed.

## Claims

### Claim 1

A power module, comprising:
a substrate including a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer;
a connection post coupled to the first conductive layer;
a conductive sheath coupled to the first conductive layer, the conductive sheath configured to receive an external connector;
a die coupled to the first conductive layer; and
a non-conducting material encapsulating the die, at least a portion of the connection post, and the conductive sheath.

### Claim 2 (depends on 1)

The power module of claim 1, further comprising a press-fit pin inserted vertically into the conductive sheath.

### Claim 3 (depends on 2)

The power module of claim 2, wherein the connection post, the conductive sheath, and the press-fit pin include copper.

### Claim 4 (depends on 2)

The power module of claim 2, wherein the conductive sheath is a hollow metal via.

### Claim 5 (depends on 1)

The power module of claim 1, wherein the connection post has a shape of a cylinder, a square pillar, a round pillar, or a hybrid pillar.

### Claim 6 (depends on 1)

The power module of claim 1, wherein the connection post and a press-fit pin form external connections to the die.

### Claim 7 (depends on 1)

The power module of claim 1, wherein the connection post is formed as a pillar that includes a cylinder coupled to a base.

### Claim 8 (depends on 7)

The power module of claim 7, wherein the cylinder and the base have cross-sections of different shapes.

### Claim 9 (depends on 1)

The power module of claim 1, further comprising a power tap disposed on the connection post.

### Claim 10

A method of forming a power module, the method comprising:
adhering a multilayer substrate to a carrier, the multilayer substrate including a first conductive layer, a second conductive layer, and an insulating layer;
disposing an external connector in a first conductive layer of the multilayer substrate;
attaching a die to the first conductive layer;
encapsulating the die and the external connector;
detaching the carrier from the multilayer substrate; and
singulating the multilayer substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein disposing the external connector in the first conductive layer includes forming a recess in the first conductive layer and inserting the external connector into the recess.

### Claim 12 (depends on 10)

The method of claim 10, wherein disposing the external connector in the first conductive layer includes disposing a connection post in the first conductive layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a power tap on the connection post.

### Claim 14 (depends on 10)

The method of claim 10, wherein disposing the external connector in the first conductive layer includes disposing a conductive sheath in the first conductive layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising inserting a press-fit pin into the conductive sheath to couple the press-fit pin to the first conductive layer.

### Claim 16 (depends on 10)

The method of claim 10, wherein encapsulating the die and the external connector includes injection molding and grinding an encapsulant.

### Claim 17

A package for an embedded semiconductor die, the package comprising:
a multilayer substrate supporting the embedded semiconductor die;
an encapsulant surrounding the embedded semiconductor die; and
a plurality of electrical connections coupling the embedded semiconductor die to the multilayer substrate, the plurality of electrical connections including:
a conductive material coupled to a surface layer of the multilayer substrate;
a connection post embedded in the surface layer; and
a press-fit pin assembly embedded in the surface layer, the press-fit pin assembly including a conductive sheath.

### Claim 18 (depends on 17)

The package of claim 17, wherein the multilayer substrate is a direct bond copper substrate including a dielectric layer between two copper layers.

### Claim 19 (depends on 17)

The package of claim 17, wherein the press-fit pin assembly includes a press-fit pin, a flat portion, and flexible metal blades.

### Claim 20 (depends on 17)

The package of claim 17, wherein the connection post is T-shaped.

### Claim 21 (depends on 17)

The package of claim 17, wherein the connection post is a solid metal via.

### Claim 22 (depends on 17)

The package of claim 17, wherein the conductive sheath is a hollow metal via.

### Claim 23 (depends on 17)

The package of claim 17, wherein the encapsulant includes a non-electrically conducting material.

### Claim 24 (depends on 17)

The package of claim 17, wherein the encapsulant includes an organic material.

### Claim 25 (depends on 17)

The package of claim 17, wherein the encapsulant includes multiple layers.

### Claim 26 (depends on 17)

The package of claim 17, further comprising one or more additional semiconductor dies.

### Claim 27 (depends on 17)

The package of claim 17, wherein the embedded semiconductor die includes at least one of silicon, silicon carbide, gallium nitride, or another compound semiconductor material, and combinations thereof.