# US 2026/0090455 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0090455 A1 - Document ID: US20260090455A1 - Status: Published application - Kind: A1 - Application number: 19/295,753 - Filed: 2025-08-11 - Published: 2026-03-26 - Earliest claimed: 2024-09-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jongwan Seo - Web page: https://patentgrep.com/patent/US20260090455A1 ## CPC - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The technical idea of the inventive concept provides a semiconductor package including a first package substrate, a second package substrate on the first package substrate, a plurality of semiconductor chips on the second package substrate, a molding member on the second package substrate and configured to surround the plurality of semiconductor chips, and a gas barrier layer on the molding member. ## Claims ### Claim 1 A semiconductor package comprising: a first package substrate; a second package substrate on the first package substrate; a plurality of semiconductor chips on the second package substrate; a molding member on the second package substrate and configured to surround the plurality of semiconductor chips; and a gas barrier layer on the molding member. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the gas barrier layer is configured to cover an upper surface of the molding member and upper surfaces of the plurality of semiconductor chips. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the gas barrier layer comprises: a first portion configured to cover an upper surface of the molding member and upper surfaces of the plurality of semiconductor chips; and a second portion configured to cover a side surface of the molding member. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the second portion of the gas barrier layer is configured to cover a side surface of the second package substrate. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the second package substrate is electrically connected to the first package substrate via substrate connection terminals, a substrate under-fill material layer configured to surround the substrate connection terminals is between the second package substrate and the first package substrate, and the gas barrier layer comprises: a first portion configured to cover an upper surface of the molding member and upper surfaces of the plurality of semiconductor chips; a second portion configured to cover a side surface of the molding member, a side surface of the second package substrate, and a side surface of the substrate under-fill material layer; and a third portion configured to cover an upper surface of the first package substrate, wherein the upper surface of the first package substrate does not vertically overlap the second package substrate. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a thickness of the gas barrier layer is 5 μm or greater. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein a water vapor transmission rate (WVTR) of the gas barrier layer is less than 1 E-3 g/m2·day. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the gas barrier layer comprises a ceramic layer further comprising at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide (SiOx), alumina (Al2O3), aluminum nitride (AlN), titanium dioxide (TiO2), zinc oxide (ZnO), and titanium nitride (TiN). ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the gas barrier layer comprises a metal layer further comprising at least one of palladium (Pd), nickel (Ni), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and zinc (Zn). ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the gas barrier layer comprises a first barrier layer and a second barrier layer stacked on the first barrier layer, and the first barrier layer and the second barrier layer are formed of different materials from each other. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein each semiconductor chip of the plurality of semiconductor chips is horizontally spaced apart from each of the other semiconductor chips of the plurality of semiconductor chips on the second package substrate, and the second package substrate is an interposer configured to electrically connect the plurality of semiconductor chips to each other. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein each semiconductor chip of the plurality of semiconductor chips is horizontally spaced apart from each of the other semiconductor chips of the plurality of semiconductor chips on the second package substrate, the second package substrate is a redistribution substrate, and the redistribution substrate comprises a silicon bridge configured to electrically connect the plurality of semiconductor chips to each other. ### Claim 13 (depends on 1) The semiconductor package of claim 1, wherein the second package substrate comprises a redistribution insulating layer and a redistribution pattern inside the redistribution insulating layer. ### Claim 14 (depends on 1) The semiconductor package of claim 1, wherein the plurality of semiconductor chips comprises an upper semiconductor chip and a lower semiconductor chip, which are vertically stacked. ### Claim 15 A semiconductor package comprising: a first package substrate; a second package substrate on the first package substrate and electrically connected to the first package substrate via substrate connection terminals; a substrate under-fill material layer between the second package substrate and the first package substrate and configured to surround the substrate connection terminals; a plurality of semiconductor chips horizontally spaced apart from each other on the second package substrate; a molding member on the second package substrate and configured to surround the plurality of semiconductor chips; a gas barrier layer comprising a first portion configured to cover an upper surface of the molding member and upper surfaces of the plurality of semiconductor chips, a second portion configured to cover a side surface of the molding member, a side surface of the second package substrate, and a side surface of the substrate under-fill material layer, and a third portion configured to cover an upper surface of the first package substrate, wherein the upper surface of the first package substrate does not vertically overlap the second package substrate; and a stiffener configured to extend in a vertical direction of the first package substrate along an edge of the first package substrate and on the third portion of the gas barrier layer. ### Claim 16 A semiconductor package comprising: a package substrate; at least one semiconductor chip on the package substrate; a molding member on the package substrate and configured to surround the at least one semiconductor chip; and a gas barrier layer between the package substrate and the molding member and between the at least one semiconductor chip and the molding member. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein a thickness of the gas barrier layer is 5 μm or greater. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein a water vapor transmission rate (WVTR) of the gas barrier layer is less than 1 E-3 g/m2·day. ### Claim 19 (depends on 16) The semiconductor package of claim 16, wherein the gas barrier layer comprises a ceramic layer further comprising at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide (SiOx), alumina (Al2O3), aluminum nitride (AlN), titanium dioxide (TiO2), zinc oxide (ZnO), and titanium nitride (TiN) or a metal layer further comprising at least one of palladium (Pd), nickel (Ni), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and zinc (Zn). ### Claim 20 (depends on 16) The semiconductor package of claim 16, wherein the gas barrier layer comprises a first barrier layer and a second barrier layer stacked on the first barrier layer, and the first barrier layer and the second barrier layer are formed of different materials from each other.