# US 2026/0090418 A1 · Semiconductor package including a conductive post > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0090418 A1 - Document ID: US20260090418A1 - Status: Published application - Kind: A1 - Application number: 19/211,600 - Filed: 2025-05-19 - Published: 2026-03-26 - Earliest claimed: 2024-09-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: HYEONJEONG HWANG; HYUNSOO CHUNG - Web page: https://patentgrep.com/patent/US20260090418A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/611: {for connecting multiple chips together} - H10W 70/69: Insulating materials thereof - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 74/016: {using moulds} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor package may include a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a conductive post on the first redistribution substrate and horizontally spaced apart from the first semiconductor chip, the conductive post having protruding portions formed on a side surface thereof, a first mold layer disposed on the first redistribution substrate and a side surface of the first semiconductor chip, and a first interface layer including a vertical portion between the first mold layer and the protruding portions of the conductive post and a horizontal portion extending from a lower end portion of the conductive post. ## Claims ### Claim 1 A semiconductor package, comprising: a first redistribution substrate; a first semiconductor chip on the first redistribution substrate; a conductive post on the first redistribution substrate and horizontally spaced apart from the first semiconductor chip, the conductive post having protruding portions formed on a side surface thereof; a first mold layer disposed on the first redistribution substrate and a side surface of the first semiconductor chip; and a first interface layer including a vertical portion between the first mold layer and the protruding portions of the conductive post and a horizontal portion extending from a lower end portion of the conductive post. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first interface layer comprises a silicon-based insulating material. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the first interface layer further comprises copper oxide. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein a thickness of the first interface layer ranges from about 1 micrometer (μm) to about 5 μm. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising a second interface layer covering a top surface of the first semiconductor chip and the side surface of the first semiconductor chip, wherein the first interface layer and the second interface layer are spaced apart from each other. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the second interface layer comprises a first portion covering the top surface of the first semiconductor chip and a second portion covering the side surface of the first semiconductor chip, and a thickness of the first portion is greater than or equal to a thickness of the second portion. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein a surface roughness of the side surface of the conductive post defining the protruding portions ranges from about 0.1 micrometers (μm) to 2 μm. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: a second redistribution substrate on the first mold layer and electrically connected to the conductive post; and a sub-semiconductor package on the second redistribution substrate, wherein the sub-semiconductor package comprises: a third redistribution substrate connected to the second redistribution substrate; a second semiconductor chip mounted on the third redistribution substrate; and a second mold layer covering the second semiconductor chip, on the third redistribution substrate. ### Claim 9 (depends on 1) The semiconductor package of claim 1, further comprising: a second redistribution substrate on the first mold layer and electrically connected to the conductive post; a third semiconductor chip mounted on the second redistribution substrate; and a third mold layer covering the third semiconductor chip, on the second redistribution substrate. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein a vertical portion of the first interface layer covers the side surface of the conductive post and the horizontal portion extends between the first mold layer and at least a portion of a top surface of the first redistribution substrate. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the horizontal portion of the first interface layer is overlapped with the first semiconductor chip, when viewed in a plan view. ### Claim 12 A semiconductor package, comprising: a first redistribution substrate; a semiconductor chip on the first redistribution substrate; a conductive post on the first redistribution substrate and horizontally spaced apart from the semiconductor chip; a mold layer provided on the first redistribution substrate and on a side surface of the semiconductor chip; and a first interface layer between the mold layer and a side surface of the conductive post, wherein the side surface of the conductive post has a first surface roughness, a top surface of the conductive post has a second surface roughness, and the second surface roughness is smaller than the first surface roughness. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the first surface roughness ranges from about 0.1 micrometers (μm) to 2 about μm. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein the second surface roughness ranges from about 0.001 micrometers (μm) to about 0.1 μm. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein a thickness of the first interface layer ranges from about 1 μm to about 5 μm. ### Claim 16 (depends on 12) The semiconductor package of claim 12, wherein the first interface layer covers the side surface of the conductive post. ### Claim 17 (depends on 12) The semiconductor package of claim 12, further comprising a second interface layer disposed on a top surface and the side surface of the semiconductor chip, wherein the first interface layer and the second interface layer are spaced apart from each other. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the second interface layer comprises a first portion covering the top surface of the semiconductor chip and a second portion covering the side surface of the semiconductor chip, and a thickness of the first portion is greater than or equal to a thickness of the second portion. ### Claim 19 A semiconductor package, comprising: a first redistribution substrate including first insulating layers and first redistribution patterns, which at least partially penetrate the first insulating layers; a semiconductor chip on the first redistribution substrate; a conductive post on the first redistribution substrate and horizontally spaced apart from the semiconductor chip, a side surface of the conductive post defined by protruding portions; a mold layer provided on the first redistribution substrate and a side surface of the semiconductor chip; a first interface layer between the mold layer and the protruding portions of the conductive post and between the mold layer and at least a portion of a top surface of the first redistribution substrate; a second redistribution substrate provided on the mold layer and electrically connected to the conductive post, the second redistribution substrate including second insulating layers and second redistribution patterns, which at least partially penetrate the second insulating layers; and an outer coupling terminal on a bottom surface of the first redistribution substrate, wherein the conductive post electrically connects the first redistribution patterns and the second redistribution patterns to each other. ### Claim 20 (depends on 19) The semiconductor package of claim 19, further comprising a second interface layer covering a top surface and the side surface of the semiconductor chip, wherein the first interface layer and the second interface layer are spaced apart from each other.