# US 2026/0090367 A1 · Semiconductor die, semiconductor package and manufacturing method of semiconductor die

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2026/0090367 A1
- Document ID: US20260090367A1
- Status: Published application
- Kind: A1
- Application number: 18/890,763
- Filed: 2024-09-20
- Published: 2026-03-26
- Earliest claimed: 2024-09-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yi-Chen Li; Jen-Yuan Chang
- Web page: https://patentgrep.com/patent/US20260090367A1

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor die including a semiconductor substrate, an interconnect structure, a capacitor structure, a redistribution layer and a bonding structure is provided. The interconnect structure is disposed on the semiconductor substrate. The capacitor structure is disposed on the interconnect structure. The redistribution layer is disposed on and electrically connected to the interconnect structure. The bonding conductor is electrically and physically in contact with the capacitor structure at a sidewall of the bonding conductor, wherein the redistribution layer is located at a lower level than the bonding conductor.

## Claims

### Claim 1

A semiconductor die, comprising:
a semiconductor substrate;
an interconnect structure disposed on the semiconductor substrate;
a capacitor structure disposed on the interconnect structure;
a redistribution layer disposed on and electrically connected to the interconnect structure; and
a bonding conductor electrically and in contact with the capacitor structure at a sidewall of the bonding conductor, wherein the redistribution layer is located at a lower level than the bonding conductor.

### Claim 2 (depends on 1)

The semiconductor die of claim 1, wherein the bonding conductor lands on and is electrically connected with the interconnect structure.

### Claim 3 (depends on 1)

The semiconductor die of claim 1, wherein a material of the redistribution layer is different from a material of the bonding conductor.

### Claim 4 (depends on 3)

The semiconductor die of claim 3, wherein the material of the redistribution layer includes aluminum, and the material of the bonding conductor includes copper.

### Claim 5 (depends on 3)

The semiconductor die of claim 3, wherein the bonding conductor lands on and is electrically connected with the redistribution layer.

### Claim 6 (depends on 3)

The semiconductor die of claim 3, further comprising:
a dielectric layer covering the redistribution layer; and
a passivation layer disposed over the dielectric layer and covering the capacitor structure.

### Claim 7 (depends on 1)

The semiconductor die of claim 1, wherein the capacitor structure comprises a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer, and the sidewall of the bonding conductor is electrically and physically in contact with one of the first electrode layer and the second electrode layer.

### Claim 8 (depends on 1)

The semiconductor die of claim 1, further comprising:
a dielectric layer laterally surrounding the bonding conductor, wherein the surface of the bonding conductor is exposed by the dielectric layer.

### Claim 9

A semiconductor package, comprising:
a first semiconductor die; and
a second semiconductor die electrically connected with the first semiconductor die, wherein the second semiconductor die includes:
a semiconductor substrate;
an interconnect structure disposed on the first semiconductor substrate;
a bonding conductor disposed on and electrically connected with the interconnect structure;
a redistribution layer disposed on the interconnect structure at a lower level than the bonding conductor; and
a capacitor structure laterally surrounding and electrically connected with a sidewall of the bonding conductor.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, further comprising:
a bonding structure electrically connected with and sandwiched between the first semiconductor die and the second semiconductor die, wherein the bonding structure is physically in contact with the bonding conductor.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein
the second semiconductor die further comprises:
a dielectric layer laterally surrounding the bonding conductor of the second semiconductor die, wherein the surface of the bonding conductor of the second semiconductor die is exposed by the dielectric layer; and
the bonding structure comprises:
a bonding conductor; and
a bonding layer laterally surrounding the bonding conductor of the bonding structure, wherein the bonding conductor of the bonding structure is physically in contact with the bonding conductor of the second semiconductor die, and the bonding layer is physically in contact with the dielectric layer.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein the bonding structure comprises a joint terminal physically in contact with the bonding conductor of the second semiconductor die.

### Claim 13 (depends on 9)

The semiconductor package of claim 9, wherein the first semiconductor die comprises:
a semiconductor substrate;
an interconnect structure disposed on the semiconductor substrate of the first semiconductor die;
a bonding conductor disposed on and electrically connected with the interconnect structure of the first semiconductor die; and
a capacitor structure laterally surrounding and electrically connected with a sidewall of the bonding conductor of the first semiconductor die.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, further comprising:
a bump connector physically in contact with the bonding conductor of the first semiconductor die.

### Claim 15 (depends on 9)

The semiconductor package of claim 9, wherein the bonding conductor of the second semiconductor die lands on and is electrically connected with the interconnect structure of the second semiconductor die.

### Claim 16 (depends on 9)

The semiconductor package of claim 9, wherein a material of the redistribution layer is different from a material of the bonding conductor of the second semiconductor die, and the bonding conductor of the second semiconductor die lands on and is electrically connected with the redistribution layer.

### Claim 17 (depends on 9)

The semiconductor package of claim 9, wherein the capacitor structure of the second semiconductor die comprises a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer, and the sidewall of the bonding conductor of the second semiconductor die is electrically and physically in contact with one of the first electrode layer and the second electrode layer.

### Claim 18

A method of manufacturing a semiconductor die, comprising:
forming an interconnect structure on a semiconductor substrate;
forming a capacitor structure over the interconnect structure;
forming a redistribution layer over and electrically connected to the interconnect structure; and
forming a bonding conductor vertically penetrating through the capacitor structure to be electrically connected with the capacitor structure at a sidewall of the bonding conductor, wherein the bonding conductor is formed at a higher level than the redistribution layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the redistribution layer is formed before forming the capacitor structure, and a material of the redistribution layer is different from a material of the bonding conductor.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
forming a passivation layer covering the capacitor structure,
wherein the redistribution layer is formed to pass through the passivation layer and electrically connected to the interconnect structure, and a material of the redistribution layer is different from a material of the bonding conductor.