# US 2026/0090366 A1 · Semiconductor device and method of forming the same

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- Number: US 2026/0090366 A1
- Document ID: US20260090366A1
- Status: Published application
- Kind: A1
- Application number: 19/201,036
- Filed: 2025-05-07
- Published: 2026-03-26
- Earliest claimed: 2024-09-18
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Shou-Te WANG
- Web page: https://patentgrep.com/patent/US20260090366A1

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/485: {Bit line contacts}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 64/01: Manufacture or treatment
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/511: {for IGFETs}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first insulating layer covering the gate structure; a contact disposed through the first insulating layer, wherein the contact is laterally adjacent to the gate structure; a metal layer disposed on the first insulating layer and in physical contact with the contact; and a first dielectric layer covering a sidewall of the metal layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a gate structure disposed on the substrate;
a first insulating layer covering the gate structure;
a contact disposed through the first insulating layer, wherein the contact is laterally adjacent to the gate structure;
a metal layer disposed on the first insulating layer and in physical contact with the contact; and
a first dielectric layer covering a sidewall of the metal layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a second insulating layer disposed on the first insulating layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a second dielectric layer disposed on a sidewall of the first dielectric layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the second dielectric layer extends through the second insulating layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the second dielectric layer covers a top portion of the gate structure.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, further comprising a third insulating layer covering the metal layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first dielectric layer and the second dielectric layer separate the sidewall of the metal layer from the third insulating layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a well region disposed within the substrate, wherein the gate structure and the contact are in physical contact with the well region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising an isolation structure disposed within the substrate, wherein the isolation structure laterally surrounds the well region.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprising:
a gate conductor disposed on the substrate;
an adhesion layer disposed on the gate conductor;
a conductive layer disposed on the adhesion layer; and
a hard mask disposed on the conductive layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the gate structure further comprising:
a spacer disposed on sidewalls of the gate conductor, the adhesion layer, the conductive layer, and the hard mask; and
a dielectric layer disposed on the surface of the spacer.

### Claim 12

A method of forming a semiconductor device, comprising:
providing a substrate;
forming a gate structure on the substrate;
forming a first insulating layer covering the gate structure;
forming a second insulating layer on the first insulating layer;
forming a metal layer on the second insulating layer; and
forming a first dielectric layer covering a sidewall of the metal layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the first dielectric layer comprises conformally depositing a first dielectric material layer, followed by etching back horizontal portions of the first dielectric material layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first dielectric material layer is deposited by atomic layer deposition.

### Claim 15 (depends on 13)

The method of claim 13, wherein an opening is formed through the second insulating layer during the etching back of the first dielectric material layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the opening exposes the gate structure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising conformally depositing a second dielectric material layer on the metal layer and the first dielectric layer, and in the opening.

### Claim 18 (depends on 17)

The method of claim 17, wherein an anisotropic etching is performed on the second dielectric material layer to form a second dielectric layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second dielectric layer covers a sidewall of the first dielectric layer and an exposed portion of the gate structure.

### Claim 20 (depends on 12)

The method of claim 12, further comprising forming a contact through the second insulating layer and the first insulating layer to electrically couple the metal layer and the substrate.