Separate metal regions in a layer of a pillar bar via on a transistor row in an integrated circuit (ic) to reduce stress and related fabrication methods

A method of fabricating an integrated circuit (IC), comprising:

• forming a substrate;
• forming transistors on the substrate in a row extending in a first direction;
• and
• forming a pillar bar comprising layers in a bar area extending over the row of transistors in a direction orthogonal to the substrate, the layers comprising:
• a top metal layer;
• a bottom metal layer coupled to a terminal of each transistor in the row of transistors;
• and
• at least one intermediate layer between the top metal layer and the bottom metal layer,
• wherein a first intermediate layer of the at least one intermediate layer comprises separate metal regions in the bar area.

An integrated circuit (IC) package comprising:

• a first IC comprising logic circuits;
• and
• a second IC comprising a power amplifier disposed on a substrate and configured to supply power to the first IC, the power amplifier comprising:
• a row of transistors disposed on the substrate and extending in a first direction;
• and
• a pillar bar comprising a stack of layers in a bar area extending over the row of transistors in a direction orthogonal to the substrate, the stack of layers comprising:
• a top metal layer;
• a bottom metal layer coupled to a terminal of each transistor in the row of transistors;
• and
• at least one intermediate layer between the top metal layer and the bottom metal layer,
• wherein a first intermediate layer of the at least one intermediate layer comprises separate metal regions in the bar area, which comprises a central area midway between a first end and a second end in the first direction.