Two-terminal mixed-ionic-electronic-conduction random access memory (miecram) device

A memory array comprising:

• a plurality of word lines;
• a plurality of bit lines intersecting the plurality of word lines at a plurality of cell locations, each bit line being paired with a corresponding complementary bit line;
• and
• a plurality of cells respectively located at the plurality of cell locations;
• wherein each cell of the plurality of cells in turn comprises:
• a memory device, the memory device in turn comprising:
• a bottom electrically conductive layer, with a mobile ionizable species, and having an electrical resistance that is less than 5 percent of the overall resistance of the memory device;
• a barrier layer, outward of the bottom electrically conductive layer and having a higher ion chemical potential relative to the bottom electrically conductive layer;
• a mixed-ionic-electronic-conduction (MIEC) switching layer, outward of the barrier layer and having an electrical conductivity dependent on ion concentration within the MIEC layer;
• and
• a top contact outward of the mixed-ionic-electronic-conduction (MIEC) switching layer, connected to a corresponding bit line;
• and
• an access transistor having a gate connected to a corresponding one of the plurality of word lines, a drain connected to the bottom electrically conductive layer, and a source connected to the corresponding complementary bit line.

A method of manufacturing an array of memory devices, comprising:

• forming a metal hydride layer;
• forming a barrier layer outward of the metal hydride layer;
• forming a mixed-ionic-electronic-conduction (MIEC) switching layer outward of the barrier layer to form a first intermediate structure;
• etching the first intermediate structure to form a plurality of devices;
• filling first dielectric material between the plurality of devices and planarizing to form a second intermediate structure;
• depositing a top contact metal layer over the second intermediate structure;
• etching the top contact metal layer to form a plurality of bit lines;
• and
• filling second dielectric material between the plurality of bit lines and planarizing.