# US 2026/0090280 A1 · Memory device

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- Number: US 2026/0090280 A1
- Document ID: US20260090280A1
- Status: Published application
- Kind: A1
- Application number: 19/408,459
- Filed: 2025-12-04
- Published: 2026-03-26
- Earliest claimed: 2016-09-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Harry-Hak-Lay Chuang; Hung Cho Wang; Tong-Chern Ong; Wen-Ting Chu; Yu-Wen Liao; Kuei-Hung Shen; Kuo-Yuan Tu; Sheng-Huang Huang
- Web page: https://patentgrep.com/patent/US20260090280A1

## CPC

- H10N 50/80: Constructional details
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/85: Materials of the active region
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a lower interconnect arranged within an inter-level dielectric (ILD) structure. An insulating structure is disposed over the ILD structure and a lower electrode is disposed between sidewalls of the insulating structure and over the lower interconnect. The lower electrode includes a material that has a planar upper surface and that continuously extends from below a topmost surface of the insulating structure to over the topmost surface of the insulating structure. A magnetic tunnel junction is over the planar upper surface of the material of the lower electrode. The magnetic tunnel junction has a pinned magnetic layer vertically separated from a free magnetic layer by a dielectric barrier layer. An upper electrode is over the magnetic tunnel junction and an upper interconnect contacts the upper electrode.

## Claims

### Claim 1

An integrated chip, comprising:
a lower interconnect arranged within an inter-level dielectric (ILD) structure;
an insulating structure disposed over the ILD structure;
a lower electrode disposed between sidewalls of the insulating structure and over the lower interconnect, wherein the lower electrode comprises a material that has a planar upper surface and that continuously extends from below a topmost surface of the insulating structure to over the topmost surface of the insulating structure;
a magnetic tunnel junction over the planar upper surface of the material of the lower electrode, the magnetic tunnel junction comprising a pinned magnetic layer vertically separated from a free magnetic layer by a dielectric barrier layer;
an upper electrode over the magnetic tunnel junction; and
an upper interconnect contacting the upper electrode.

### Claim 2 (depends on 1)

The integrated chip of claim 1, wherein the insulating structure has a larger height above the lower interconnect than laterally outside of the lower interconnect.

### Claim 3 (depends on 1)

The integrated chip of claim 1, further comprising:
one or more sidewall spacers arranged along first sides and opposing second sides of the magnetic tunnel junction and the upper electrode, wherein the one or more sidewall spacers have a larger height along the first sides than along the second sides.

### Claim 4 (depends on 1)

The integrated chip of claim 1, wherein the upper interconnect is laterally off-centered from the upper electrode.

### Claim 5 (depends on 4)

The integrated chip of claim 4, further comprising:
one or more sidewall spacers arranged along first sides and opposing second sides of the magnetic tunnel junction and the upper electrode, wherein the upper interconnect covers a top of the one or more sidewall spacers along the first sides and wherein the top of the one or more sidewall spacers along the second sides is laterally outside of the upper interconnect.

### Claim 6 (depends on 1)

The integrated chip of claim 1, wherein the lower electrode has a chemically mechanically planarized upper surface.

### Claim 7 (depends on 1)

The integrated chip of claim 1, wherein the lower interconnect comprises a conductive core surrounded by a barrier, the ILD structure surrounding a lower part of the barrier and the insulating structure laterally surrounding an upper part of the barrier.

### Claim 8 (depends on 7)

The integrated chip of claim 7, wherein the magnetic tunnel junction is directly above a topmost surface of the conductive core.

### Claim 9 (depends on 7)

The integrated chip of claim 7, wherein the lower electrode comprises titanium nitride, the barrier comprises tantalum nitride, the conductive core comprises copper, and the insulating structure comprises silicon carbide.

### Claim 10 (depends on 1)

The integrated chip of claim 1, further comprising:
a peripheral via laterally separated from the magnetic tunnel junction by the ILD structure, wherein the peripheral via vertically extends from below the magnetic tunnel junction to laterally adjacent to the magnetic tunnel junction.

### Claim 11

An integrated chip, comprising:
a lower insulating structure arranged over a substrate;
a lower conductor comprising a lower segment extending through the lower insulating structure and an upper segment extending outward from one or more sides of the lower segment to over the lower insulating structure;
a passivation structure arranged along a lower surface and sidewalls of the lower conductor, wherein the passivation structure has a rounded surface that is above a top of the lower insulating structure and below the lower conductor;
a switching structure over the lower conductor; and
an upper conductor over the switching structure.

### Claim 12 (depends on 11)

The integrated chip of claim 11, wherein a topmost height of the passivation structure is along the rounded surface.

### Claim 13 (depends on 11)

The integrated chip of claim 11, wherein the rounded surface is embedded within the lower conductor.

### Claim 14 (depends on 11)

The integrated chip of claim 11, wherein the lower conductor has a minimum thickness directly above the rounded surface.

### Claim 15 (depends on 14)

The integrated chip of claim 14, wherein a thickness of the lower conductor increases in opposing directions away from the minimum thickness.

### Claim 16 (depends on 11)

The integrated chip of claim 11, further comprising:
a lower interconnect arranged within a lower inter-level dielectric layer vertically between the substrate and the lower insulating structure, wherein the switching structure is substantially centered over the lower interconnect.

### Claim 17

An integrated chip, comprising:
a dielectric structure disposed over a substrate, the dielectric structure having an upper surface facing away from the substrate;
a first conductive structure disposed between sidewalls of the dielectric structure and above the dielectric structure, the first conductive structure having an upper surface facing away from the substrate, the upper surface of the first conductive structure being more planar than the upper surface of the dielectric structure;
a magnetic tunnel junction over the first conductive structure; and
a second conductive structure over the magnetic tunnel junction.

### Claim 18 (depends on 17)

The integrated chip of claim 17, wherein the upper surface of the first conductive structure extends laterally past one or more protuberances extending outward from the dielectric structure.

### Claim 19 (depends on 17)

The integrated chip of claim 17, wherein the first conductive structure is substantially symmetric about a vertical line bisecting the upper surface of the first conductive structure.

### Claim 20 (depends on 17)

The integrated chip of claim 17,
wherein the first conductive structure comprises a central region arranged between the sidewalls of the dielectric structure and peripheral regions over the upper surface of the dielectric structure; and
wherein lower surfaces of the first conductive structure within the peripheral regions have recesses surrounding the central region.