# US 2026/0090102 A1 · Active matrix substrate and display device

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- Number: US 2026/0090102 A1
- Document ID: US20260090102A1
- Status: Published application
- Kind: A1
- Application number: 19/333,623
- Filed: 2025-09-19
- Published: 2026-03-26
- Earliest claimed: 2024-09-20
- Assignees: Sharp Display Technology Corporation
- Applicants: Sharp Display Technology Corporation
- Inventors: Kengo HARA; Tohru Daitoh; Hajime Imai; Teruyuki Ueda; Tatsuya Kawasaki
- Web page: https://patentgrep.com/patent/US20260090102A1

## CPC

- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs. Each of the oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a source contact region, and a drain contact region, a lower gate electrode, and an upper gate electrode. In a plan view, when a protrusion width of the lower gate electrode from the upper gate electrode toward the source contact region is referred to as a first protrusion width, a protrusion width of the lower gate electrode from the upper gate electrode toward the drain contact region is referred to as a second protrusion width, and a sum of the first protrusion width and the second protrusion width is referred to as a third protrusion width, the plurality of oxide semiconductor include a first TFT and a second TFT having the third protrusion widths different from each other.

## Claims

### Claim 1

An active matrix substrate comprising:
a substrate; and
a plurality of oxide semiconductor TFTs supported by the substrate,
wherein each of the plurality of oxide semiconductor TFTs includes
an oxide semiconductor layer including a channel region, and a source contact region and a drain contact region located on a respective one of both sides of the channel region,
a lower gate electrode disposed between the substrate and the oxide semiconductor layer, and
an upper gate electrode disposed on the opposite side of the lower gate electrode with respect to the oxide semiconductor layer, and
in a plan view, when a protrusion width of the lower gate electrode from the upper gate electrode toward the source contact region is referred to as a first protrusion width, a protrusion width of the lower gate electrode from the upper gate electrode toward the drain contact region is referred to as a second protrusion width, and a sum of the first protrusion width and the second protrusion width is referred to as a third protrusion width,
the plurality of oxide semiconductor TFTs include a first TFT and a second TFT having the third protrusion widths different from each other.

### Claim 2 (depends on 1)

The active matrix substrate according to claim 1,
wherein a width of the upper gate electrode of the first TFT along a channel length direction is substantially the same as a width of the upper gate electrode of the second TFT along the channel length direction.

### Claim 3 (depends on 1)

The active matrix substrate according to claim 1,
wherein the third protrusion width of the first TFT is larger than the third protrusion width of the second TFT.

### Claim 4 (depends on 3)

The active matrix substrate according to claim 3,
wherein each of the first protrusion width and the second protrusion width of the first TFT is 1 μm or more.

### Claim 5 (depends on 3)

The active matrix substrate according to claim 3,
wherein each of the first protrusion width and the second protrusion width of the first TFT is 2 μm or less.

### Claim 6 (depends on 3)

The active matrix substrate according to claim 3,
wherein each of the first protrusion width and the second protrusion width of the second TFT is 0 μm or less.

### Claim 7 (depends on 3)

The active matrix substrate according to claim 3,
wherein each of the plurality of oxide semiconductor TFTs further includes
a lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, and
an upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, and
in a plan view, when a protrusion width of the upper gate insulating layer from the upper gate electrode toward the source contact region is referred to as a fourth protrusion width and a protrusion width of the upper gate insulating layer from the upper gate electrode toward the drain contact region is referred to as a fifth protrusion width,
each of the fourth protrusion width and the fifth protrusion width of the first TFT is 0.5μm or less, and
each of the fourth protrusion width and the fifth protrusion width of the second TFT is 1μm or more.

### Claim 8 (depends on 3)

The active matrix substrate according to claim 3,
wherein each of the plurality of oxide semiconductor TFTs further includes
a lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, and
an upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, and
when two edges of the upper gate insulating layer each located at a respective one of both ends in a channel length direction are referred to as a first edge and a second edge, respectively, and two edges of the lower gate electrode each located at a respective one of both ends in the channel length direction are referred to as a third edge and a fourth edge, respectively,
the first edge and the second edge of the upper gate insulating layer of the first TFT are located closer to the inside in the channel length direction than the third edge and the fourth edge, respectively, of the lower gate electrode of the first TFT, and
the first edge and the second edge of the upper gate insulating layer of the second TFT are located closer to the outside in the channel length direction than the third edge and the fourth edge, respectively, of the lower gate electrode of the second TFT.

### Claim 9 (depends on 3)

The active matrix substrate according to claim 3,
wherein the oxide semiconductor layer of the first TFT is formed in the same layer as the oxide semiconductor layer of the second TFT.

### Claim 10 (depends on 3)

The active matrix substrate according to claim 3,
wherein the oxide semiconductor layer of the first TFT is formed in a layer different from the oxide semiconductor layer of the second TFT, and
mobility of the oxide semiconductor layer of the first TFT is higher than mobility of the oxide semiconductor layer of the second TFT.

### Claim 11 (depends on 1)

The active matrix substrate according to claim 1,
wherein the plurality of oxide semiconductor TFTs include an oxide semiconductor TFT having the second protrusion width larger than the first protrusion width.

### Claim 12 (depends on 1)

The active matrix substrate according to claim 1,
wherein the oxide semiconductor layer includes an In-Ga-Zn-O based semiconductor.

### Claim 13 (depends on 10)

The active matrix substrate according to claim 10,
wherein each of the oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT includes In and/or Sn, and
a sum of atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the second TFT is smaller than a sum of atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the first TFT.

### Claim 14 (depends on 10)

The active matrix substrate according to claim 10,
wherein both the oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT include an In-Ga-Zn-O based semiconductor, and
an atomic ratio of In to all metal elements in the second oxide semiconductor layer is smaller than an atomic ratio of In to all metal elements in the oxide semiconductor layer of the first TFT.

### Claim 15 (depends on 1)

A display device comprising:
the active matrix substrate according to claim 1.

### Claim 16 (depends on 15)

The display device according to claim 15,
wherein the display device is a liquid crystal display device.

### Claim 17 (depends on 15)

The display device according to claim 15,
wherein the display device is an organic EL display device.