# US 2026/0090100 A1 · Integrated gate-all-around (gaa)/finfet transistor devices

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- Number: US 2026/0090100 A1
- Document ID: US20260090100A1
- Status: Published application
- Kind: A1
- Application number: 18/893,950
- Filed: 2024-09-23
- Published: 2026-03-26
- Earliest claimed: 2024-09-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chen-Guan Lee; Hsu-Yu Chang; Rahul Ramaswamy; Chia-Hong Jan
- Web page: https://patentgrep.com/patent/US20260090100A1

## CPC

- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/215: {comprising FinFETs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/40: FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In embodiments of the present disclosure, an integrated transistor device includes a gate-all-around (GAA) transistor and a FinFET transistor device on the same substrate. The FinFET transistor includes a dielectric region between the channel of the FinFET transistor and the substrate.

## Claims

### Claim 1

An apparatus comprising:
a substrate;
a first transistor on the substrate, the first transistor comprising:
a plurality of first channel regions; and
a first gate region surrounding each of the first channel regions;
a second transistor on the substrate, the second transistor comprising:
a second channel region;
a second gate region around at least three sides of the second channel region; and
a dielectric region comprising Oxygen between the second gate region and the second channel region and further between the second channel region and the substrate.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first channel regions are above a first sub-fin extending from the substrate and the second channel region is above a second sub-fin extending from the substrate.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the dielectric region comprising Oxygen surrounds the second channel region.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein each of the substrate, the first channel regions, and the second channel region are semiconductor materials comprising Silicon.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the first transistor comprises epitaxial regions adjacent opposite sides of the first channel regions; and
the second transistor comprises epitaxial regions adjacent opposite sides of the second channel region.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein each of the epitaxial regions is on the substrate.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the dielectric region is a first dielectric region, and the second transistor further comprises second dielectric regions between the first dielectric region and the epitaxial regions of the second transistor.

### Claim 8 (depends on 1)

An integrated circuit device assembly comprising a circuit board and the apparatus of claim 1.

### Claim 9 (depends on 8)

A system comprising the integrated circuit device assembly of claim 8 and one or more memory devices.

### Claim 10

An integrated circuit device comprising:
a semiconductor layer;
a first transistor on the semiconductor layer, the first transistor comprising:
a plurality of semiconductor channel regions above the semiconductor layer, the channel regions connecting a source region of the first transistor and a drain region of the first transistor; and
a conductive gate region surrounding each of the channel regions; and
a second transistor on the semiconductor layer, the second transistor comprising:
a fin extending from the semiconductor layer, the fin comprising a channel region; and
a conductive gate region around the fin;
wherein the fin comprises a dielectric between the channel region and the semiconductor layer.

### Claim 11 (depends on 10)

The integrated circuit device of claim 10, wherein the dielectric surrounds the channel region of the second transistor.

### Claim 12 (depends on 10)

The integrated circuit device of claim 10, wherein dielectric comprises Oxygen.

### Claim 13 (depends on 10)

The integrated circuit device of claim 10, wherein each of the semiconductor layer, the channel regions of the first transistor, and the channel region of the second transistor are semiconductor materials comprising Silicon.

### Claim 14 (depends on 10)

The integrated circuit device of claim 10, wherein:
the first transistor comprises epitaxial regions adjacent opposite sides of its channel regions; and
the second transistor comprises epitaxial regions adjacent opposite sides of its channel region;
wherein each of the epitaxial regions is on the semiconductor layer.

### Claim 15 (depends on 14)

The integrated circuit device of claim 14, wherein the dielectric is a first dielectric, and the second transistor comprises a second dielectric between the first dielectric and the epitaxial regions of the second transistor.

### Claim 16

An integrated circuit device comprising:
a semiconductor substrate;
a gate-all-around (GAA) transistor on the semiconductor substrate; and
a FinFET transistor on the semiconductor substrate, the FinFET comprising a dielectric region between a gate region and a channel region of the FinFET transistor and further between the channel region and the substrate.

### Claim 17 (depends on 16)

The integrated circuit device of claim 16, wherein the dielectric region of the FinFET transistor surrounds the channel region.

### Claim 18 (depends on 16)

The integrated circuit device of claim 16, wherein the dielectric region of the FinFET transistor comprises Oxygen.

### Claim 19 (depends on 16)

A processor comprising the integrated circuit device of claim 16.

### Claim 20 (depends on 19)

A system comprising the processor of claim 19 and one or more memory devices.