# US 2026/0089986 A1 · Semiconductor device and fabricating method thereof

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- Number: US 2026/0089986 A1
- Document ID: US20260089986A1
- Status: Published application
- Kind: A1
- Application number: 18/956,009
- Filed: 2024-11-22
- Published: 2026-03-26
- Earliest claimed: 2024-09-24
- Assignees: Hon Hai Precision Industry Co., Ltd.
- Applicants: Hon Hai Precision Industry Co., Ltd.
- Inventors: Jheng-Sheng YOU; Han-Chin CHIU
- Web page: https://patentgrep.com/patent/US20260089986A1

## CPC

- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A fabricating method of a semiconductor device includes performing a first patterning process to form a first trench in a substrate structure. The substrate structure includes a substrate and a compound semiconductor layer over the substrate. The first patterning process is performed such that the first trench passes through the compound semiconductor layer and exposes the substrate. The fabricating method further includes forming a capacitor structure in the first trench. Forming the capacitor structure includes: forming a first metal layer lining the first trench and in contact with the substrate; forming a first dielectric layer lining the first metal layer and in contact with the first metal layer; and forming a second metal layer lining the first dielectric layer and in contact with the first dielectric layer.

## Claims

### Claim 1

A fabricating method of a semiconductor device, comprising:
performing a first patterning process to form a first trench in a substrate structure, wherein the substrate structure comprises a substrate and a compound semiconductor layer over the substrate, and the first trench passes through the compound semiconductor layer and exposes the substrate; and
forming a capacitor structure in the first trench, wherein forming the capacitor structure comprises:
forming a first metal layer lining the first trench and in contact with the substrate;
forming a first dielectric layer lining the first metal layer and in contact with the first metal layer; and
forming a second metal layer lining the first dielectric layer and in contact with the first dielectric layer.

### Claim 2 (depends on 1)

The fabricating method of claim 1, wherein the substrate structure comprises a transistor and the first metal layer is formed such that the first metal layer extends from over the transistor along the first trench to a side of the transistor.

### Claim 3 (depends on 2)

The fabricating method of claim 2, wherein the first metal layer is formed such that a first portion of the first metal layer is at the side of the transistor and in contact with the substrate, and a top surface of the first portion of the first metal layer is lower than a top surface of the compound semiconductor layer.

### Claim 4 (depends on 3)

The fabricating method of claim 3, wherein the first metal layer is formed such that a bottom surface of the first portion of the first metal layer is lower than a top surface of the substrate.

### Claim 5 (depends on 3)

The fabricating method of claim 3, wherein the first dielectric layer is formed such that the first dielectric layer is partially lower than the top surface of the compound semiconductor layer.

### Claim 6 (depends on 2)

The fabricating method of claim 2, wherein the first metal layer is formed such that a second portion of the first metal layer is electrically connected to a source/drain contact of the transistor through a through via.

### Claim 7 (depends on 6)

The fabricating method of claim 6, wherein the second metal layer is completely higher than a top surface of the compound semiconductor layer.

### Claim 8 (depends on 6)

The fabricating method of claim 6, wherein forming the capacitor structure further comprises:
forming a second dielectric layer lining the second metal layer and in contact with the second metal layer; and
forming a third metal layer lining the second dielectric layer and in contact with the second dielectric layer.

### Claim 9 (depends on 1)

The fabricating method of claim 1, wherein the second metal layer is partially lower than a top surface of the compound semiconductor layer.

### Claim 10 (depends on 1)

The fabricating method of claim 1, wherein:
performing the first patterning process further comprises forming a second trench in the substrate structure and exposing the substrate;
forming the capacitor structure further comprises:
forming the first metal layer such that the first metal layer is lining the second trench; and
after the first metal layer is formed, performing a second patterning process to the first metal layer to remove a portion of the first metal layer that is in the second trench to re-expose the substrate through the second trench; and
the fabricating method further comprises performing a scribing process through the second trench.

### Claim 11

A semiconductor device, comprising:
a substrate structure comprising a substrate and a compound semiconductor layer over the substrate; and
a capacitor structure over the substrate structure and comprising:
a first metal layer having a first portion extending downward through the compound semiconductor layer and in contact with the substrate;
a first dielectric layer over the first metal layer and lining the first portion of the first metal layer; and
a second metal layer over the first portion of the first metal layer, over the first dielectric layer, and lining the first dielectric layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising a second dielectric layer and a third metal layer, wherein the second dielectric layer is over the second metal layer and lining the second metal layer, and the third metal layer is over the second dielectric layer and lining the second dielectric layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the second metal layer, the second dielectric layer, and the third metal layer are completely higher than a top surface of the compound semiconductor layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein a bottom surface of the first portion of the first metal layer is lower than a top surface of the substrate.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein a top surface of the first portion of the first metal layer is lower than a top surface of the compound semiconductor layer.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the first dielectric layer is partially lower than a top surface of the compound semiconductor layer.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the second metal layer is completely higher than a top surface of the compound semiconductor layer.

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the second metal layer is partially lower than a top surface of the compound semiconductor layer.

### Claim 19 (depends on 11)

The semiconductor device of claim 11, wherein the substrate structure comprises a transistor and a second portion of the first metal layer is over the transistor and is electrically connected to a source/drain contact of the transistor through a through via.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the first portion of the first metal layer is at a side of the transistor.