# US 2026/0089984 A1 · Inductors having a high quality factor manufactured using deep trench isolation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0089984 A1 - Document ID: US20260089984A1 - Status: Published application - Kind: A1 - Application number: 18/959,789 - Filed: 2024-11-26 - Published: 2026-03-26 - Earliest claimed: 2024-09-25 - Assignees: Microchip Technology Incorporated - Applicants: Microchip Technology Incorporated - Inventors: Mazhar Hoque; Amit Rai; Samir Fuke; Joseph Rascon; Randy Yach - Web page: https://patentgrep.com/patent/US20260089984A1 ## CPC - H10D 1/64: Variable-capacitance diodes, e.g. varactors - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 1/20: Inductors - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 1/68: Capacitors having no potential barriers - H10D 84/201: {characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits} - H10D 84/204: {of combinations of diodes or capacitors or resistors} - H10D 84/60: characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs (H10D84/40 takes precedence) - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus, system, and method for the manufacturing of an inductor having a high quality factor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include an inductor coil above a surface of the substrate. The apparatus may further include a trench etched in the substrate, a dielectric in the trench, and a conductor within the dielectric in the trench. The conductor may be biased to create a depletion region below the inductor coil. ## Claims ### Claim 1 An apparatus, comprising: a substrate doped to form a well; an inductor coil above a surface of the substrate; a trench etched in the substrate; a dielectric in the trench; and a conductor within the dielectric in the trench, the conductor biased to create a depletion region below the inductor coil. ### Claim 2 (depends on 1) The apparatus of claim 1, comprising: an n-well surrounding the substrate to isolate the substrate; and wherein the substrate is biased. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein at least one of a length, a width, or a depth of the trench is selected based on a strength of an eddy current created by the inductor coil. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein at least one of a length, a width, or a depth of the conductor is selected based on a strength of an eddy current created by the inductor coil. ### Claim 5 (depends on 1) The apparatus of claim 1, comprising: a second trench etched on the surface of the substrate; a second dielectric in the trench; and a second conductor in the second dielectric in the trench, the second conductor biased to create a second depletion region below the inductor coil; wherein a spacing between the trench and the second trench is such that the depletion region and the second depletion region remain separate. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the second trench is substantially parallel to the trench. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the spacing between the trench and the second trench is based on a strength of an eddy current created by the inductor coil. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising: a silicon base; and an insulator layered on the silicon base; wherein the substrate is layered on the insulator. ### Claim 9 A method, comprising: etching a trench in a substrate, the substrate doped to form a well; forming an inductor coil above a surface of the substrate; filling the trench with a dielectric; and placing a conductor within the dielectric, the conductor biased to create a depletion region below the inductor coil. ### Claim 10 (depends on 9) The method of claim 9, comprising: isolating the substrate using an n-well surrounding the substrate; and biasing the substrate. ### Claim 11 (depends on 9) The method of claim 9, wherein at least one of a length, a width, or a depth of the trench is selected based on a strength of an eddy current created by the inductor coil. ### Claim 12 (depends on 9) The method of claim 9, wherein at least one of a length, a width, or a depth of the conductor is selected based on a strength of an eddy current created by the inductor coil. ### Claim 13 (depends on 9) The method of claim 9, comprising: etching a second trench on the surface of the substrate; filling the second trench with a second dielectric; and placing a second conductor in the second dielectric in the trench, the second conductor biased to create a second depletion region below the inductor coil; wherein a spacing between the trench and the second trench is such that the depletion region and the second depletion region remain separate. ### Claim 14 (depends on 13) The method of claim 13, wherein the second trench is substantially parallel to the trench. ### Claim 15 (depends on 13) The method of claim 13, wherein the spacing between the trench and the second trench is based on a strength of an eddy current created by the inductor coil. ### Claim 16 (depends on 9) The method of claim 9, wherein: layering the substrate on an insulator; and layering the insulator on a silicon base. ### Claim 17 An inductor made by a process comprising: etching a trench in a substrate, the substrate doped to form a well; forming an inductor coil above a surface of the substrate; filling the trench with a dielectric; and placing a conductor within the dielectric, the conductor biased to create a depletion region below the inductor coil. ### Claim 18 (depends on 17) The inductor of claim 17, the process comprising: isolating the substrate using an n-well surrounding the substrate; and biasing the substrate. ### Claim 19 (depends on 17) The inductor of claim 17, wherein at least one of a length, a width, or a depth of the trench or at least one of a length, a width, or a depth of the conductor is selected based on a strength of an eddy current created by the inductor coil. ### Claim 20 (depends on 17) The inductor of claim 17, the process comprising: etching a second trench on the surface of the substrate; filling the second trench with a second dielectric; and placing a second conductor in the second dielectric in the trench, the second conductor biased to create a second depletion region below the inductor coil; wherein a spacing between the trench and the second trench is such that the depletion region and the second depletion region remain separate.